參數(shù)資料
型號: ADSP-2196MKSTZ-160
廠商: Analog Devices Inc
文件頁數(shù): 1/68頁
文件大小: 0K
描述: IC DSP CONTROLLER 16BIT 144-LQFP
標準包裝: 1
系列: ADSP-21xx
類型: 定點
接口: 主機接口,SPI,SSP,UART
時鐘速率: 160MHz
非易失內(nèi)存: ROM(48 kB)
芯片上RAM: 40kB
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 2.50V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 144-LQFP
供應商設備封裝: 144-LQFP(20x20)
包裝: 托盤
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Preliminary Technical Data
DSP Microcomputer
This information applies to a product under development. Its characteristics
and specifications are subject to change without notice. Analog Devices
assumes no obligation regarding future manufacturing unless otherwise
agreed to in writing.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel:781/329-4700
World Wide Web Site: http://www.analog.com
Fax:781/326-8703
Analog Devices,Inc., 2001
REV. PrA
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ADSP-2196
ADSP-219x DSP CORE FEATURES
6.25 ns Instruction Cycle Time (Internal), for up to
160 MIPS Sustained Performance
ADSP-218x Family Code Compatible with the Same
Easy -to-Use Algebraic Syntax
Single-Cycle Instruction Execution
Up to 16M words of Addressable Memory Space with
24 Bits of Addressing Width
Dual Purpose Program Memory for Both Instruction and
Data Storage
Fully Transparent Instruction Cache Allows Dual
Operand Fetches in Every Instruction Cycle
Unified Memory Space Permits Flexible Address
Generation, Using Two Independent DAG Units
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units with Dual 40-bit
Accumulators
Single-Cycle Context Switch between Two Sets of
Computational and DAG Registers
Parallel Execution of Computation and Memory
Instructions
Pipelined Architecture Supports Efficient Code
Execution at Speeds up to 160 MIPS
Register File Computations with All Nonconditional,
Nonparallel Computational Instructions
Powerful Program Sequencer Provides Zero-Overhead
Looping and Conditional Instruction Execution
Architectural Enhancements for Compiled C
Code Efficiency
FUNCTIONAL BLOCK DIAGRAM
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