- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄1900 > ADSP-2196MKSTZ-160 (Analog Devices Inc)IC DSP CONTROLLER 16BIT 144-LQFP PDF資料下載
參數(shù)資料
| 型號(hào)： | ADSP-2196MKSTZ-160 |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 3/68頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CONTROLLER 16BIT 144-LQFP |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | ADSP-21xx |
| 類(lèi)型： | 定點(diǎn) |
| 接口： | 主機(jī)接口，SPI，SSP，UART |
| 時(shí)鐘速率： | 160MHz |
| 非易失內(nèi)存： | ROM（48 kB） |
| 芯片上RAM： | 40kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 2.50V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類(lèi)型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-LQFP（20x20） |
| 包裝： | 托盤(pán) |
第1頁(yè)第2頁(yè)當(dāng)前第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
11
REV. PrA
For current information contact Analog Devices at 800/262-5643
ADSP-2196
September 2001
35(/,0,1$5< 7(&+1,&$/ '$7$
Two mode bits in the Host Port configuration register
HPCR [7:6] define the functionality of the HACK line.
HPCR6 is initialized at reset based on the values driven on
HACK and HACK_P pins (shown in Table 5); HPCR7 is
always cleared (0) at reset. HPCR [7:6] can be modified
after reset by a write access to the host port
configuration register.
The functional modes selected by HPCR [7:6] are as follows
(assuming active high signal):
ACK Mode—Acknowledge is active on strobes; HACK
goes high from the leading edge of the strobe to indicate
when the access can complete. After the Host samples the
HACK active, it can complete the access by removing the
strobe.The host port then removes the HACK.
Ready Mode—Ready active on strobes, goes low to insert
wait state during the access.If the host port can not
complete the access, it de-asserts the HACK/READY
line. In this case, the Host has to extend the access by
keeping the strobe asserted. When the Host samples the
HACK asserted, it can then proceed and complete the
access by de-asserting the strobe.
While in Address Cycle Control (ACC) mode and the ACK
or Ready acknowledge modes, the HACK is returned active
for any address cycle.
Host Port Chip Selects
There are two chip-select signals associated with the Host
Port: HCMS and HCIOMS. The Host Chip Memory
Select (HCMS) lets the Host select the DSP and directly
access the DSP’s internal/external memory space or boot
memory space. The Host Chip I/O Memory Select
(HCIOMS) lets the Host select the DSP and directly access
the DSP’s internal I/O memory space.
Before starting a direct access, the Host configures Host
port interface registers, specifying the width of external data
bus (8- or 16-bit) and the target address page (in the IJPG
register). The DSP generates the needed memory select
signals during the access, based on the target address. The
Host port interface combines the data from one, two, or
three consecutive Host accesses (up to one 24-bit value) into
a single DMA bus access to prefetch Host direct reads or to
post direct writes. During assembly of larger words, the Host
port interface asserts ACK for each byte access that does
not start a read or complete a write. Otherwise, the Host
port interface asserts ACK when it has completed the
memory access successfully.
DSP Serial Ports (SPORTs)
The ADSP-2196 incorporates three complete synchronous
serial ports (SPORT0, SPORT1, and SPORT2) for serial
and multiprocessor communications. The SPORTs
support the following features:
Bidirectional operation—each SPORT has independent
transmit and receive pins.
Buffered (8-deep) transmit and receive ports—each port
has a data register for transferring data words to and from
other DSP components and shift registers for shifting data
in and out of the data registers.
Clocking—each transmit and receive port can either use
an external serial clock (
≤75 MHz) or generate its own,
in frequencies ranging from 1144 Hz to 75 MHz.
Word length—each SPORT supports serial data words
from 3 to 16 bits in length transferred in Big Endian
(MSB) or Little Endian (LSB) format.
Framing—each transmit and receive port can run with or
without frame sync signals for each data word. Frame sync
signals can be generated internally or externally, active
high or low, and with either of two pulsewidths and early
or late frame sync.
Companding in hardware—each SPORT can perform
A-law or -law companding according to ITU recommen-
dation G.711. Companding can be selected on the
transmit and/or receive channel of the SPORT without
additional latencies.
DMA operations with single-cycle overhead—each
SPORT can automatically receive and transmit multiple
buffers of memory data, one data word each DSP cycle.
Either the DSP’s core or a Host processor can link or chain
sequences of DMA transfers between a SPORT and
memory. The chained DMA can be dynamically allocated
and updated through the DMA descriptors (DMA
transfer parameters) that set up the chain.
Interrupts—each transmit and receive port generates an
interrupt upon completing the transfer of a data word or
after transferring an entire data buffer or buffers through
DMA.
Multichannel capability—each SPORT supports the
H.100 standard.
Table 5. Host Port Acknowledge Mode Selection
Values Driven At
Reset
HPCR [7:6]
Initial Values
Acknowledge
Mode
HACK_P
HACK
Bit 7
Bit 6
0
1
Ready Mode
01
0
ACK Mode
10
0
ACK Mode
1
0
1
Ready Mode
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| ADSP-21990BSTZ | IC DSP CONTROLLER 16BIT 176-LQFP |
| ADSP-21991BSTZ | IC DSP CONTROLLER 16BIT 176-LQFP |
| ADSP-21992YBC | IC DSP CTLR 16BIT 196CSPBGA |
| ADSP-3PARCBF548M01 | MODULE BOARD BF548 |
| ADSP-BF506KSWZ-4F | IC DSP 12BIT 400MHZ 120LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| ADSP-21990BBC | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 150MHz 150MIPS 196-Pin Mini-BGA 制造商:Rochester Electronics LLC 功能描述:160 MIPS, MIXED SIGNAL DSPWITH 14-BIT - Bulk |
| ADSP-21990BST | 制造商:Rochester Electronics LLC 功能描述:160 MIPS,MIXED SIGNAL DSP WITH 14BIT - Tape and Reel |
| ADSP-21990BSTZ | 功能描述:IC DSP CONTROLLER 16BIT 176-LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:ADSP-21xx 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類(lèi)型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類(lèi)型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤(pán) |
| ADSP-21991BBC | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 150MHz 150MIPS 196-Pin Mini-BGA |
| ADSP-21991BBCZ | 功能描述:IC DSP CTLR 16BIT 196CSPBGA RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - DSP（數(shù)字式信號(hào)處理器） 系列:ADSP-21xx 標(biāo)準(zhǔn)包裝:2 系列:StarCore 類(lèi)型:SC140 內(nèi)核 接口:DSI，以太網(wǎng)，RS-232 時(shí)鐘速率:400MHz 非易失內(nèi)存:外部 芯片上RAM:1.436MB 電壓 - 輸入/輸出:3.30V 電壓 - 核心:1.20V 工作溫度:-40°C ~ 105°C 安裝類(lèi)型:表面貼裝 封裝/外殼:431-BFBGA，F(xiàn)CBGA 供應(yīng)商設(shè)備封裝:431-FCPBGA（20x20） 包裝:托盤(pán) |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。