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| 型號： | ADSP-2196MKSTZ-160 |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 56/68頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC DSP CONTROLLER 16BIT 144-LQFP |
| 標準包裝： | 1 |
| 系列： | ADSP-21xx |
| 類型： | 定點 |
| 接口： | 主機接口，SPI，SSP，UART |
| 時鐘速率： | 160MHz |
| 非易失內(nèi)存： | ROM（48 kB） |
| 芯片上RAM： | 40kB |
| 電壓 - 輸入/輸出： | 3.30V |
| 電壓 - 核心： | 2.50V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 144-LQFP |
| 供應(yīng)商設(shè)備封裝： | 144-LQFP（20x20） |
| 包裝： | 托盤 |
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For current information contact Analog Devices at 800/262-5643
ADSP-2196
September 2001
This information applies to a product under development. Its characteristics and specifications are subject to change with-
out notice. Analog Devices assumes no obligation regarding future manufacturing unless otherwise agreed to in writing.
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a peripheral to one of the 12 user-defined interrupts. These
assignments determine the priority of each peripheral for
interrupt service.
There are three serial ports on the ADSP-2196 that provide
a complete synchronous, full-duplex serial interface. This
interface includes optional companding in hardware and a
wide variety of framed or frameless data transmit and receive
modes of operation. Each serial port can transmit or receive
an internal or external, programmable serial clock and
frame syncs. Each serial port supports 128-channel Time
Division Multiplexing.
The ADSP-2196 provides up to sixteen general-purpose
I/O pins, which are programmable as either inputs or
outputs. Eight of these pins are dedicated general purpose
Programmable Flag pins. The other eight of them are mul-
tifunctional pins, acting as general purpose I/O pins when
the DSP connects to an 8-bit external data bus and acting
as the upper eight data pins when the DSP connects to a
16-bit external data bus. These Programmable Flag pins can
implement edge- or level-sensitive interrupts, some of which
can be used to base the execution of conditional
instructions.
Three programmable interval timers generate periodic
interrupts. Each timer can be independently set to operate
in one of three modes:
Pulse Waveform Generation mode
Pulsewidth Count/Capture mode
External Event Watchdog mode
Each timer has one bi-directional pin and four registers that
implement its mode of operation: A 7-bit configuration
register, a 32-bit count register, a 32-bit period register, and
a 32-bit pulsewidth register. A single status register supports
all three timers. A bit in the mode status register globally
enables or disables all three timers, and a bit in each timer’s
configuration register enables or disables the corresponding
timer independently of the others.
Memory Architecture
The ADSP-2196 DSP provides 16K words of on-chip
SRAM memory. This memory is divided into two 8K blocks
located on memory Page 0 in the DSP’s memory map. The
DSP also provides 16K words of on-chip ROM. In addition
to the internal and external memory space, the ADSP-2196
can address two additional and separate off-chip memory
spaces: I/O space and boot space.
As shown in Figure 2, the DSP’s two internal memory
blocks populate all of Page 0. The entire DSP memory map
consists of 256 pages (Pages 0
255), and each page is 64K
words long. External memory space consists of four
memory banks (banks 0–3) and supports a wide variety of
SRAM memory devices. Each bank is selectable using the
memory select pins (MS3–0) and has configurable page
boundaries, waitstates, and waitstate modes. The 1K word
of on-chip boot-ROM populates the top of Page 255 while
the remaining 254 pages are addressable off-chip. I/O
memory pages differ from external memory pages in that
I/O pages are 1K word long, and the external I/O pages have
their own select pin (IOMS). Pages 0–31 of I/O memory
space reside on-chip and contain the configuration registers
for the peripherals. Both the ADSP-2196 and DMA-capa-
ble peripherals can access the DSP’s entire memory map.
Internal (On-Chip) Memory
The ADSP-2196’s unified program and data memory space
consists of 16M locations that are accessible through two
24-bit address buses, the PMA and DMA buses. The DSP
uses slightly different mechanisms to generate a 24-bit
address for each bus. The DSP has three functions that
support access to the full memory map.
The DAGs generate 24-bit addresses for data fetches from
the entire DSP memory address range. Because DAG
index (address) registers are 16 bits wide and hold the
lower 16 bits of the address, each of the DAGs has its own
8-bit page register (DMPGx) to hold the most significant
eight address bits. Before a DAG generates an address,
the program must set the DAG’s DMPGx register to the
appropriate memory page.
The Program Sequencer generates the addresses for
instruction fetches. For relative addressing instructions,
the program sequencer bases addresses for relative jumps,
calls, and loops on the 24-bit Program Counter (PC). In
direct addressing instructions (two-word instructions),
the instruction provides an immediate 24-bit address
value. The PC allows linear addressing of the full 24-bit
address range.
For indirect jumps and calls that use a 16-bit DAG
address register for part of the branch address, the
Program Sequencer relies on an 8-bit Indirect Jump page
(IJPG) register to supply the most significant eight
address bits. Before a cross page jump or call, the program
must set the program sequencer’s IJPG register to the
appropriate memory page.
The ADSP-2196 has 1K word of on-chip ROM that holds
boot routines. If peripheral booting is selected, the DSP
starts executing instructions from the on-chip boot ROM,
which starts the boot process from the selected peripheral.
on-chip boot ROM is located on Page 255 in the DSP’s
memory space map.
Internal On-Chip ROM
The ADSP-2196 DSP features a 16K-word × 24-bit
on-chip maskable ROM mapped into program memory
space (Figure 3).
Customers can arrange to have the ROM programmed with
application-specific code.
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| ADSP-21990BBC | 制造商:Analog Devices 功能描述:DSP Fixed-Point 16-Bit 150MHz 150MIPS 196-Pin Mini-BGA 制造商:Rochester Electronics LLC 功能描述:160 MIPS, MIXED SIGNAL DSPWITH 14-BIT - Bulk |
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