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參數(shù)資料
| 型號： | ADMC328 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 28-Lead ROM-Based DSP Motor Controller(28腳含ROM、數(shù)字信號處理的的馬達控制器) |
| 中文描述： | 28 - ROM的鉛基于DSP的電機控制器（28腳含光盤，數(shù)字信號處理的的馬達控制器） |
| 文件頁數(shù)： | 23/36頁 |
| 文件大?。?/td> | 470K |
| 代理商： | ADMC328 |
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PRELIMINARY TECHNICAL DATA ADMC328
–23–
REV. A
individual bits that must be set to enable the various
interrupt sources. If any peripheral interrupt is to be
enabled, the
IRQ2
interrupt enable bit (bit 9) of the
IMASK register must be set. T he configuration of the
IMASK register of the ADMC328 is shown at the end of
the data sheet.
Interrupt Configuration
T he IFC and ICNT L registers of the DSP core control
and configure the interrupt controller of the DSP core.
T he IFC register is a 16-bit register that may be used to
force and/or clear any of the eight DSP interrupts. Bits 0
to 7 of the IFC register may be used to clear the DSP
interrupts while Bits 8 to 15 can be used to force a corre-
sponding interrupt. Writing to Bits 11 and 12 in IFC is the
only way to create the two software interrupts.
T he ICNT L register is used to configure the sensitivity
(edge or level) of the
IRQ0
,
IRQ1
and
IRQ2
interrupts
and to enable/disable interrupt nesting. Setting bit 0 of
ICNT L configures the
IRQ0
as edge-sensitive, while clear-
ing the bit configures it for level-sensitive. Bit 1 is used to
configure the
IRQ1
interrupt. Bit 2 is used to configure the
IRQ2
interrupt. It is recommended that the
IRQ2
interrupt
always be configured as level-sensitive to ensures that no
peripheral interrupts are lost. Setting bit 4 of the ICNT L
register enables interrupt nesting. T he configuration of
both the IFC and ICNT L registers is shown at the end of
the data sheet.
Interrupt Operation
Following a reset, the ROM code on the ADMC328 must
copy a default interrupt vector table into program memory
RAM from address 0x0000 to 0x002F. Since each inter-
rupt source has a dedicated four-word space in this vector
table, it is possible to code short interrupt service routines
(ISR) in place. Alternatively, it may be necessary to insert
a JUMP instruction to the appropriate start address of the
interrupt service routine if more memory is required for
the ISR.
When an interrupt occurs, the program sequencer ensures
that there is no latency (beyond synchronization delay)
when processing unmasked interrupts. In the case of the
timer, SPORT 1, and software interrupts, the interrupt
controller automatically jumps to the appropriate location
in the interrupt vector table. At this point, a JUMP in-
struction to the appropriate ISR is required.
Motor control peripheral interrupt are slightly different.
When a peripheral interrupt is detected, a bit is set in the
IRQFLAG register for PWMSYNC and
PWMTRIP
or in
the PIOFL AG0, or PIOFL AG1 registers for a PIO inter-
rupt, and the
IRQ2
line is pulled low until all pending
interrupts are acknowledged. For any of the peripheral
interrupts, the interrupt controller automatically jumps to
location 0x0004 in the interrupt vector table. Code which
is automatically loaded into location 0x0004 on reset,
subsequently reads the IRQFLAG register to determine if
the source of the interrupt was a PWM trip, a PWMSYNC
or a PIO and jumps to the appropriate interrupt vector
location.
T he code automatically loaded at location 0x0004 by the
monitor on reset should be:
0x0004:ASTAT = DM(IRQFLAG);
DM(IRQFLAG_SAVE) = ASTAT;
IF EQ JUMP 0x002C
IF LT JUMP 0x000C;
At this point, a JUMP instruction to the appropriate ISR,
at the interrupt vector location shown in T able IX , is re-
quired. If more than one interrupt occurs simultaneously,
the higher priority interrupt service routine is executed.
Reading the IRQFLAG register clears the
PWMTRIP
and
PWMSYNC bits and acknowledges the interrupt, thus
allowing further interrupts when the ISR exits. When the
IRQFLAG register is read, it is saved in a data memory
variable so the user ISR can check to see if there are simul-
taneous PWMSYNC and
PWMTRIP
interrupts.
A user’s PIO interrupt service routine must read the
PIOFLAG0, and PIOFLAG1 registers to determine which
PIO port is the source of the interrupt. Reading
PIOFL AG0, and PIOFLAG1 registers clear all bits in the
registers and acknowledge the interrupt, thus allowing
further interrupts when the ISR exits.
T he configuration of all these registers is shown at the end
of the data sheet.
SYSTEM CONTROLLER
T he system controller block of the ADMC328 performs
the following functions:
1.
Manages the interface and data transfer between the
DSP core and the motor control peripherals.
2.
Handles interrupts generated by the motor control
peripherals and generates a DSP core interrupt signal
IRQ2
.
3.
Controls the ADC multiplexer select lines.
4.
Enables
PWMTRIP
and PWMSYNC interrupts.
5.
Controls the multiplexing of the SPORT 1 pins to se-
lect either DR1A or DR1B data receive pins. It also
allows configuration of SPORT 1 as a UART interface.
6.
Controls the PWM single/double update mode.
7.
Controls the ADC conversion time modes.
8.
Controls the auxiliary PWM operation mode.
9.
Contains a status register (SYSST AT ) that indicates
the state of the
PWMTRIP
pin, the watchdog timer,
and the PWM timer.
10. Performs a reset of the motor control peripherals and
control registers following a hardware, software or
watchdog initiated reset.
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| ADMC401-ADVEVALKIT | Circular Connector; No. of Contacts:5; Series:MS27497; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:10; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:10-5 RoHS Compliant: No |
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| ADMC328TN | 制造商:AD 制造商全稱:Analog Devices 功能描述:28-Lead ROM-Based DSP Motor Controller with Current Sense |
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| ADMC328TR-XXX-YY | 制造商:AD 制造商全稱:Analog Devices 功能描述:28-Lead ROM-Based DSP Motor Controller with Current Sense |
| ADMC328YN | 制造商:AD 制造商全稱:Analog Devices 功能描述:28-Lead ROM-Based DSP Motor Controller with Current Sense |
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