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參數資料
| 型號： | ADMC328 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 28-Lead ROM-Based DSP Motor Controller(28腳含ROM、數字信號處理的的馬達控制器) |
| 中文描述： | 28 - ROM的鉛基于DSP的電機控制器（28腳含光盤，數字信號處理的的馬達控制器） |
| 文件頁數： | 12/36頁 |
| 文件大小： | 470K |
| 代理商： | ADMC328 |
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ADMC328
–12–
REV. A
Each of the six PWM output signals can be enabled or
disabled by separate output enable bits of the PWMSEG
register. In addition, three control bits of the PWMSEG
register permit crossover of the two signals of a PWM pair
for easy control of ECM or BDCM. In crossover mode,
the PWM signal destined for the high side switch is di-
verted to the complementary low side output and the signal
destined for the low side switch is diverted to the corre-
sponding high side output signal.
In many applications, there is a need to provide an isola-
tion barrier in the gate-drive circuits that turn on the power
devices of the inverter. In general, there are two common
isolation techniques: optical isolation using opto-couplers,
and transformer isolation using pulse transformers. T he
PWM controller of the ADMC328 permits mixing of the
output PWM signals with a high frequency chopping signal
to permit an easy interface to such pulse transformers.
T he features of this gate-drive chopping mode can be
controlled by the PWMGAT E register. T here is an 8-bit
value within the PWMGAT E register that directly controls
the chopping frequency. In addition, high frequency chopping
can be independently enabled for the high side and the low
side outputs using separate control bits in the PWMGAT E
register.
T he PWM generator is capable of operating in two distinct
modes: single update mode or double update mode. In
single update mode, the duty cycle values are program-
mable only once per PWM period, so that the resultant
PWM patterns are symmetrical about the midpoint of the
PWM period. In the double update mode, a second updat-
ing of the PWM duty cycle values is implemented at the
midpoint of the PWM period. In this mode, it is possible to
produce asymmetrical PWM patterns, that produce lower
harmonic distortion in three-phase PWM inverters. T his
technique also permits the closed loop controller to change
the average voltage applied to the machine winding at a
faster rate allowing wider closed loop bandwidths to be
achieved. T he operating mode of the PWM block (single
or double update mode) is selected by a control bit in
MODECT RL register.
T he PWM generator of the ADMC328 also provides an
internal signal which synchronizes the PWM switching
frequency to the A/D operation. In single update mode, a
PWMSYNC pulse is produced at the start of each PWM
period. In double update mode, an additional PWMSYNC
pulse is produced at the mid-point of each PWM period.
T he width of the PWMSYNC pulse is programmable
through the PWMSYNCWT register.
T he PWM signals produced by the ADMC328 can be
shut-off in a number of different ways. First, there is a
dedicated asynchronous PWM shutdown pin,
PWMTRIP
,
which, when brought LO, instantaneously places all six
PWM outputs in the OFF state. In addition, PWM shut-
down is initiated when the voltage on the analog input pin
(I
SENSE
) is pulled 550mV below ground corresponding to
an over current fault. Because these two hardware shut-
down mechanisms are asynchronous, and the associated
PWM disable circuitry does not use clocked logic, the
PWM will shutdown even if the DSP clock is not running.
T he PWM system may also be shutdown from software by
writing to the PWMSWT register.
Status information about the PWM system of the
ADMC328 is available to the user in the SYSST AT regis-
ter. In particular, the state of the
PWMTRIP
is available,
as well as a status bit that indicates whether operation is in
the first half or the second half of the PWM period.
A functional block diagram of the PWM controller is
shown in Figure 6. T he generation of the six output PWM
signals on pins AH to CL is controlled by four important
blocks:
T he three-phase PWM timing unit, which is the core of
the PWM controller, generates three pairs of comple-
mented and dead time adjusted center based PWM sig-
nals.
T he output control unit allows the redirection of the
outputs of the three-phase timing unit for each channel
to either the high side or the low side output. In addi-
tion, the output control unit allows individual enabling/
disabling of each of the six PWM output signals.
T he GAT E drive unit provides the high chopping fre-
quency and its subsequent mixing with the PWM signals.
T he PWM shutdown controller manages the three PWM
shutdown modes (via the
PWMTRIP
pin, the analog
block or the PWMSWT register) and generates the cor-
rect
RESET
signal for the T iming Unit
T he PWM controller is driven by a clock at the same
frequency as the DSP instruction rate, CLK OUT , and is
capable of generating two interrupts to the DSP core.
One interrupt is generated on the occurrence of a
PWMSYNC pulse and the other is generated on the
occurrence of any PWM shutdown action.
Three-Phase Timing Unit
T he 16-bit three-phase timing unit is the core of the PWM
controller and produces three pairs of pulsewidth modu-
lated signals with high resolution and minimal processor
overhead. T here are four main configuration registers
(PWMT M, PWMDT , PWMPD and PWMSYNCWT ) that
determine the fundamental characteristics of the PWM
outputs. In addition, the operating mode of the PWM
(single or double update mode) is selected by bit 6 of the
MODECT RL register. T hese registers in conjunction with
the three 16-bit duty cycle registers (PWMCHA,
PWMCHB and PWMCHC) control the output of the
three-phase timing unit.
PWM Switching Frequency: PWMTM Register
T he PWM switching frequency is controlled by the PWM
period register, PWMT M. T he fundamental timing unit of
the PWM controller is t
= 1/f
where f
is the
CLK OUT frequency (DSP instruction rate). T herefore, for
a 20 MHz CLK OUT , the fundamental time increment is
50 ns. T he value written to the PWMT M register is effec-
tively the number of t
clock increments in half a PWM
period. T he required PWMT M value is a function of the
desired PWM switching frequency (f
PWM
) and is given by:
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