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參數(shù)資料
| 型號(hào)： | ADMC328 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 28-Lead ROM-Based DSP Motor Controller(28腳含ROM、數(shù)字信號(hào)處理的的馬達(dá)控制器) |
| 中文描述： | 28 - ROM的鉛基于DSP的電機(jī)控制器（28腳含光盤，數(shù)字信號(hào)處理的的馬達(dá)控制器） |
| 文件頁數(shù)： | 18/36頁 |
| 文件大?。?/td> | 470K |
| 代理商： | ADMC328 |
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ADMC328
–18–
REV. A
three phase timing unit will resume and the new duty-cycle
values will be latched on the next PWMSYNC boundary.
PWM Registers
T he configuration of the PWM registers is described at the
end of the data sheet.
ADC OVERVIEW
A
nalog Function Block
T he analog input block of the ADMC328 consists of an A/
D converter, a current sense amplifier and trip circuit, and
an internal voltage reference circuit. T here are six analog
input signal pins on the ADMC328. T he signals on two
pins V1 and V2 are connected directly to the A/D converter
channels V1 and V2. T he signal on the I
SENSE
pin is con-
nected to a by to an inverting amplifier with a gain of five
which feeds the ISENSE channel of the A/D converter.
T he output of the current amplifier also generates a
PWMTRIP
signal when its inputs falls below 550 mV. T he
remaining three inputs on VAUX 0, VAUX 1 and VAUX 2
are fed to the VAUX A/D channel via an input multiplexer.
Finally, the 2% 2.5V reference output can also be selected
as the VAUX A/D channel via the input multiplexer. T he
VAUX input multiplexer is controlled using the
ADCMUX 0 and ADCMUX 1 bits of the MODECT RL
register (T able VI).
T he A/D converter is a 4-channel, single slope analog data
acquisition system which uses a 12-bit data register. Data
conversion is performed by measuring the crossover time
between the analog input signals and the sawtooth refer-
ence ramp. T here are four simple voltage comparators
which detect each crossover and latch each timed counter
value into a channel-specific output register. T his allows
four conversions to be performed by the ADC between
successive PWMSYNC pulses. T he sawtooth reference
ramp is generated by charging an external capacitor from
the ADMC328 programmable current source. T he calibra-
tion value captured by converting the 2% reference output
can be used to determine the current source setting to
compensate the reference ramp for capacitor and current
source tolerances.
Table VI. ADC Auxiliary Channel Selection
MODECTRL (1)
ADCMUX1
0
0
1
1
MODECTRL (0)
ADCMUX0
0
1
0
1
Select
VAUX 0
VAUX 1
VAUX 2
Calibration (V
REF
)
Analog Block
T he operation of the ADC block will be explained using
Figures 11 and 12. T he reference ramp is tied to one input
of each of the four comparators. T his reference ramp is
generated by charging an external timing capacitor with a
constant current source. T he timing capacitor is connected
between pins ICONST and GND. T he capacitor voltage is
reset at the start of each PWMSYNC pulse, which by de-
fault is held high for 40 CLK OUT cycles (T
CRST
= 2.0 μs for
a 20 MHz CLK OUT ). On the falling edge of PWMSYNC,
the capacitor begins to charge at a rate determined by the
values of the capacitor and the current source. T he internal
current source is connected to the external timing capaci-
tor from pin ICONST . An external current source could
also be used, if required. T he four input comparators of the
ADC block continuously compare the values of the four
analog inputs with the capacitor voltage. Each comparator
output will go high when the capacitor voltage exceeds its
analog input voltage.
ADC Timer Block
T he ADC timer block is simply four 12-bit counters
clocked at a rate determined by the ADCCNT bit (bit 7) in
the MODECT RL register. If ADCCNT is cleared, the
counters are clocked at the CLK IN rate, or if ADC C NT is
set, the counter is clocked by C L K OUT . T hus, at the
maximum CLK OUT frequency of 20 MHz, this results in
a timer resolution of 100 ns if ADC C NT is cleared, or
50 ns, if ADCCNT is set.
C
GND
VAUX0
VAUX1
VAUX2
V2L
VAUXL
4-1
MUX
V1
PW MSYNC (CONVST)
ADC
REGISTERS
V1L
V3L
V2
ISENSE
MODECTRL <I0...I3>
(CAP
RESET)
CLK MODECTRL<7>
12-Bit
ADC
TIMER
BLOCK
C OMP
PW MTRIPB
0.8 X
VREF
C OM P
C OMP
C OMP
C OMP
ADC registers
ADC1
ADC2
ADC3
ADCAUX
MODECTRL<0..1>
-5 X
External
C harging
C ap
Vc
Figure 11. ADC overview
Each counter is reset during the high PWMSYNC pulse so
that the counter begins counting at the beginning of the
reference voltage ramp. When the output of each compara-
tor goes high, the counter value is latched into the appro-
priate 12-bit ADC register. T here are four pair of ADC
registers (ADC 1, ADC 2, ADC 3 and ADCAUX ) corre-
sponding to each of the four comparators. Each
comparator’s register pair is organized as master/slave, also
called master/shadow. At the end of each reference voltage
ramp, which is prior to the next PWMSYNC, all four mas-
ter registers will have been loaded with the new conversion
count. At the rising edge of the PWMSYNC, the registered
conversion count for each channel is loaded into the DSP-
readable shadow registers, ADC 1, ADC2, ADC3, and
ADCAUX . T he controller will then read these shadow
registers containing the previous PWM period conversion
count, while internally the master registers will be loaded
with the current PWM period conversion count.
T he first set of values loaded into the output registers after
the first PWMSYNC interrupt will be invalid because the
latched value is indeterminate. Also, if the input analog
voltage exceeds the peak capacitor ramp voltage, the com-
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| ADMC401-ADVEVALKIT | Circular Connector; No. of Contacts:5; Series:MS27497; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:10; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:10-5 RoHS Compliant: No |
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