參數(shù)資料
型號(hào)： ADMC328
廠商： Analog Devices, Inc.
英文描述： 28-Lead ROM-Based DSP Motor Controller(28腳含ROM、數(shù)字信號(hào)處理的的馬達(dá)控制器)
中文描述： 28 - ROM的鉛基于DSP的電機(jī)控制器（28腳含光盤，數(shù)字信號(hào)處理的的馬達(dá)控制器）
文件頁(yè)數(shù)： 19/36頁(yè)
文件大小： 470K
代理商： ADMC328
PRELIMINARY TECHNICAL DATA ADMC328
–19–
REV. A
parator output will be permanently low and a 0xFFF0 code
will be produced. T his indicates an input overvoltage con-
dition.
V1
PWMSYNC
V
VIL
COMPARATOR
OUTPUT
t
V
C
V
CMAX
T
CRST
t
VIL
T
PW M
- T
CR ST
Figure 12. Analog input block operation
ADC Resolution
Because the operation of the ADC is intrinsically linked to
the PWM block, the effective resolution of the ADC is a
function of the PWM switching frequency. T he effective
ADC resolution is determined by the rate at which the
counter timer is clocked. T he counter clock rate, as stated
above, is controlled by ADCCNT bit (bit 7) of the
MODECT RL register. For a CLK OUT period of t
CK
and
a PWM period of T
PWM
, the maximum count of the ADC
is given by:
Max Count = min (4095, (T
PWM
– T
CRST
)/2 t
CK
)
for MODECT RL Bit 7 = 0
Max Count = min (4095, (T
PWM
– T
CRST
)/t
CK
)
for MODECT RL Bit 7 = 1
Where T
PWM
is equal to the PWM period if operating in
single update mode, or it is equal to half that period if op-
erating in double update mode. For an assumed CLK OUT
frequency of 20 MHz and PWMSYNC pulsewidth of 2.0
μs, the effective resolution of the ADC block is tabulated
for various PWM switching frequencies in T able VII.
Table VII. ADC Resolution Examples
PWM
MODECTRL[7] = 0
Freq.
Max
Effective
(kHz)
Count
Resolution
MODECTRL[7] = 1
Max
Count
Effective
Resolution
2.5
4
8
18
24
4095
3230
1605
702
521
12
4095
4095
3210
1404
1043
12
12
>11
>10
>9
>9
>11
>10
>10
External Timing Capacitor
In order to maximize the useful input voltage range and
effective resolution of the ADC, it is necessary to select the
value of the external timing capacitor. For a given capaci-
tance value, Cnom, the peak ramp voltage is given by:
(
)
T
T
nom
Cnom
P W M
C R ST
V
C max
IC ON ST
=
×
where ICONST
nom
is the nominal current source value of
100 μA and T
CRST
is the PWMSYNC pulse width. When
the appropriate capacitor is used, it will be possible to pro-
gram the current source to compensate for its variation in
the nominal value and the capacitor tolerance.
Table VIII. Timing capacitor selection
PWM Frequency
PWM Frequency
(kHz)
MODECTRL[7] = 0 MODECTRL[7] = 1
Timing
Capacitor
(pF)
(kHz)
2.1–2.7
2.7–3.2
3.2–3.9
3.9–4.7
4.7–5.6
5.6–6.7
6.7–8.0
8.0–9.5
9.5–11.5
11.5–14.1
14.1–17.1
17.1–20.4
20.4–25.3
25.3–30.1
4.2–5.2
5.2–6.3
6.3–7.7
7.7–9.2
9.2–11.2
11.2–13.3
13.3–16.0
16.0–18.8
18.8–23.0
23.0–28.1
28.1–34.1
34.1–40.8
40.8–50.6
50.6–60.2
1500
1200
1000
820
680
560
470
390
330
270
220
180
150
120
Programmable C urrent Source
T he ADMC328 has an internal current source which is
used to charge an external capacitor, generating the voltage
ramp used for conversion. T he magnitude of the output of
the current source circuit is subject to manufacturing varia-
tions and can vary from one device to the next. T herefore,
the ADMC328 incudes a programmable current source
whose output can always be tuned to within 5% of the
target 100μA. A 3-bit register, ICONST _T RIM, allows
the user to make this adjustment. T he output current is
proportional to the value written to the register: 0x0 pro-
duces the minimum output, and 0x7 produces the maxi-
mum output. T he default value of ICONST _T RIM after
reset us 0x0. Because of manufacturing variations, the
minimum current source output for any particular part can
range from 64μA to 100μA. Similarly, the maximum out-
put can range from 10μA to 155 μA.
ADC Reference Ramp C alibration
T he programmable current source can be used to compen-
sate the reference ramp slope for both the current source
manufacturing variations and the external charging capaci-
tor tolerance. T he current source calibration sets the refer-
ence ramp to within 5% of its target slope. T he following is
a brief description of a simple calibration algorithm which
can be implemented in the user’s code. T he target refer-
ence ramp, shown in Figure 13, is matched to the 0.3V -
3.5V signal range of the ADC comparators. Since the de-
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