參數(shù)資料
型號： ADMC328
廠商： Analog Devices, Inc.
英文描述： 28-Lead ROM-Based DSP Motor Controller(28腳含ROM、數(shù)字信號處理的的馬達控制器)
中文描述： 28 - ROM的鉛基于DSP的電機控制器（28腳含光盤，數(shù)字信號處理的的馬達控制器）
文件頁數(shù)： 21/36頁
文件大小： 470K
代理商： ADMC328
PRELIMINARY TECHNICAL DATA ADMC328
–21–
REV. A
rate (or 2 t
CK
) so that the corresponding switching periods
are given by:
T
AUX 0
=
2
3
(AUX T M0 + 1)
3
t
CK
T
AUX 1
= 2
3
(AUX T M1 + 1)
3
t
CK
Since the values in both AUX T M0 and AUX T M1 can
range from 0 to 0xFF, the achievable switching frequency
of the auxiliary PWM signals may range from 39.1 kHz to
10 MHz for a CLK OUT frequency of 20 MHz.
T he on-time of the two auxiliary PWM signals is pro-
grammed by the two 8-bit AUX CH0 and AUX CH1 regis-
ters, according to:
T
ON
,
AUX 0
= 2
3
(AUX CH0)
3
t
CK
T
ON
,
AUX 1
= 2
3
(AUX CH1)
3
t
CK
so that output duty cycles from 0% to 100% are possible.
Duty cycles of 100% are produced if the on-time value
exceeds the period value. T ypical auxiliary PWM wave-
forms in independent mode are shown in Figure 16(a).
When bit 8 of the MODECT RL register is cleared, the
auxiliary PWM channels are placed in offset mode. In
offset mode, the switching frequency of the two signals on
the AUX 0 and AUX 1 pins are identical and controlled by
AUX T M0 in a manner similar to that previously described
for independent mode. In addition, the on times of both
the AUX 0 and AUX 1 signals are controlled by the
AUX CH0 and AUX CH1 registers as before. However, in
this mode the AUX T M1 register defines the offset time
from the rising edge of the signal on the AUX 0 pin to that
on the AUX 1 pin according to:
T
OFFSET
= 2
3
(AUX T M1 + 1)
3
t
CK
For correct operation in this mode, the value written to the
AUX T M1 register must be less than the value written to
the AUX T M0 register. T ypical auxiliary PWM waveforms
in offset mode are shown in Figure 16(b). Again, duty
cycles from 0% to 100% are possible in this mode.
In both operating modes, the resolution of the auxiliary
PWM system is 8-bit only at the minimum switching
frequency (AUX T M0 = AUX T M1 = 255 in independent
mode, AUX T M0 = 255 in offset mode). Obviously, as the
switching frequency is increased the resolution is reduced.
Values can be written to the auxiliary PWM registers at any
time. However, new duty cycle values written to the
AUX CH0 and AUX CH1 registers only become effective at
the start of the next cycle. Writing to the AUX T M0 or
AUX T M1 registers cause the internal timers to be reset to
0 and new PWM cycles begin.
By default following a reset, bit 8 of the MODEC T RL
register is cleared thus enabling offset mode. In addition,
the registers AUX T M0 and AUX T M1 default to 0xFF,
corresponding to the minimum switching frequency and
zero offset. T he on-time registers AUX C H0 and
AUX CH1 default to 0x00.
AUX0
AUX1
AUX0
AUX1
2
3
(AUXTM 1 + 1)
2
3
(AUXTM0 + 1)
2
3
AUXCH0
2
3
(AUXTM 0 + 1)
2
3
AUXCH1
2
3
(AUXTM0 + 1)
2
3
(AUXTM1 + 1)
(a)
(b)
2
3
AUXCH1
2
3
AUXCH1
2
3
AUXCH0
Figure 16. Typical auxiliary PWM signals in
(a) independent mode, and
(b) offset mode. (All times in increments of t
CK.
)
Auxiliary PWM Interface, Registers and Pins
T he registers of the auxiliary PWM system are summarized
at the end of the data sheet.
PWM DAC Equation
T he auxiliary PWM output can be filtered in order to pro-
duce a low frequency analog signal between 0 V to 5.0V dc.
For example, a 2-pole filter with a 1.2 kHz cutoff frequency
will sufficiently attenuate the PWM carrier. Figure 17
shows how the filter would be applied.
C1
C2
R1
R2
R1 = R2 = 13k
V
C1 = C2 = 10nF
AUXPW M
Figure 17. Auxiliary PWM output filter
WATCHDOG TIMER
T he ADMC328 incorporates a watchdog timer that can
perform a full reset of the DSP and motor control peripher-
als in the event of software error. T he watchdog timer is
enabled by writing a timeout value to the 16-bit
WDT IMER register. T he timeout value represents the
number of CLK IN cycles required for the watchdog timer
to count down to zero. When the watchdog timer reaches
zero, a full DSP core and motor control peripheral reset is
performed. In addition, Bit 1 of the SYSST AT register is set
so that after a watchdog reset the ADMC328 can deter-
mine that the reset was due to the timeout of the watchdog
timer and not an external reset. Following a watchdog
reset, bit 1 of the SYSST AT register may be cleared by
writing zero to the WDT IMER register. T his clears the
status bit but does not enable the watchdog timer.
On reset, the watchdog timer is disabled and is only en-
abled when the first timeout value is written to the
WDT IMER register. T o prevent the watchdog timer from
timing out, the user must write to the WDT IMER register at
regular intervals (shorter than the programmed WDT IMER
period value). On all but the first write to WDT IMER, the
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