參數(shù)資料
型號(hào)： ADE7758ARWZRL
廠(chǎng)商： ANALOG DEVICES INC
元件分類(lèi)： 模擬信號(hào)調(diào)理
英文描述： Poly Phase Multifunction Energy Metering IC with Per Phase Information
中文描述： SPECIALTY ANALOG CIRCUIT, PDSO24
封裝： LEAD FREE, MS-013-AD, SOIC-24
文件頁(yè)數(shù)： 65/68頁(yè)
文件大?。?/td> 1584K
代理商： ADE7758ARWZRL
ADE7758
INTERRUPT MASK REGISTER (0x18)
When an interrupt event occurs in the ADE7758, the IRQ logic output goes active low if the mask bit for this event is Logic 1 in the
MASK register. The IRQ logic output is reset to its default collector open state when the RSTATUS register is read. Table 19 describes the
function of each bit in the interrupt mask register.
Table 19. Function of Each Bit in the Interrupt Mask Register
Bit
Location
Flag
Value
Description
Enables an interrupt when there is a change in Bit 14 of any one of the three WATTHR registers,
i.e., the WATTHR register is half full.
Enables an interrupt when there is a change in Bit 14 of any one of the three VARHR registers,
i.e., the VARHR register is half full.
Enables an interrupt when there is a 0 to 1 transition in the MSB of any one of the three VAHR
registers, i.e., the VAHR register is half full.
3
SAGA
0
Enables an interrupt when there is a SAG on the line voltage of the Phase A.
4
SAGB
0
Enables an interrupt when there is a SAG on the line voltage of the Phase B.
5
SAGC
0
Enables an interrupt when there is a SAG on the line voltage of the Phase C.
6
ZXTOA
0
Enables an interrupt when there is a zero-crossing timeout detection on Phase A.
7
ZXTOB
0
Enables an interrupt when there is a zero-crossing timeout detection on Phase B.
8
ZXTOC
0
Enables an interrupt when there is a zero-crossing timeout detection on Phase C.
Enables an interrupt when there is a zero crossing in the voltage channel of Phase A (see the
Zero-Crossing Detection section).
Enables an interrupt when there is a zero crossing in the voltage channel of Phase B (see the
Zero-Crossing Detection section).
Enables an interrupt when there is a zero crossing in the voltage channel of Phase C (see the
Zero-Crossing Detection section).
12
LENERGY
0
Enables an interrupt when the energy accumulations over LINECYC are finished.
13
RESERVED
0
Reserved.
Enables an interrupt when the voltage input selected in the MMODE register is above the value
in the PKVLVL register.
Enables an interrupt when the current input selected in the MMODE register is above the value
in the PKILVL register.
16
WFSM
0
Enables an interrupt when data is present in the WAVEMODE register.
Enables an interrupt when there is a sign change in the watt calculation among any one of the
phases specified by the TERMSEL bits in the COMPMODE register.
Enables an interrupt when there is a sign change in the VAR calculation among any one of the
phases specified by the TERMSEL bits in the COMPMODE register.
Enables an interrupt when the zero crossing from Phase A is not followed by the zero crossing
of Phase C but with that of Phase B.
Rev. A | Page 65 of 68
Interrupt
Default
0
AEHF
0
1
REHF
0
2
VAEHF
0
9
ZXA
0
10
ZXB
0
11
ZXC
0
14
PKV
0
15
PKI
0
17
REVPAP
0
18
REVPRP
0
19
SEQERR
0
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