參數(shù)資料
型號： ADE7753
廠商： Analog Devices, Inc.
英文描述： Active and Apparent Energy Metering IC with di/dt sensor interface
中文描述： 主動與迪視電能計量IC / dt的傳感器接口
文件頁數(shù)： 31/38頁
文件大小： 449K
代理商： ADE7753
ADE7753
–31–
REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
A ddress
Name
R/W
# of Bits
Default
Description
10h
PH C AL
R /W
6 bits
0D h
Phase Calibration register. T he phase relationship between
Channel 1 and 2 can be adjusted by writing to this 6-bit register.
T he valid content of this 2's compliment register is between 1Dh
to 21h. At line frequency of 60Hz, this is a range from -2.06 to
+0.7 degrees. —see
Phase Compensation
.
Active Power Offset Correction. T his 16-bit register allows small
offsets in the Active Power Calculation to be removed – see
Active Power Calculation
.
Power Gain Adjust. T his is a 12-bit register. T he Active Power
calculation can be calibrated by writing to this register. T he
calibration range is ±50% of the nominal full scale active power.
T he resolution of the gain adjust is 0.0244% / LSB—see
Channel
1 ADC Gain Adjust
.
Active Energy divider register. T he internal active energy register
is divided by the value of this register before being stored in the
AENERGY register.
CF Frequency Divider Numerator register. T he output frequency
on the CF pin is adjusted by writing to this 12-bit read/write
register – see
Energy to Frequency Conversion.
CF Frequency Divider Denominator register. T he output
frequency on the CF pin is adjusted by writing to this 12-bit
read/write register – see
Energy to Frequency Conversion.
Channel 1 RMS value (current channel).
Channel 2 RMS value (voltage channel).
Channel 1 RMS offset correction register
Channel 2 RMS offset correction register
Apparent Gain register. Apparent power calculation can be
calibrated by writing this register. T he calibration range is 50%
of the nominal full scale real power. T he resolution of the gain
adjust is 0.02444% / LSB.
Apparent Energy divider register. T he internal apparent energy
register is divided by the value of this register before being stored
in the VAENERGY register.
L ine Cycle Energy Accumulation Mode L ine-Cycle register.
T his 15-bit register is used during line cycle energy
accumulation mode to set the number of half line cycles for
energy accumulation - see
Line Cycle Energy Accumulation Mode
.
Zero-cross T ime Out. If no zero crossings are detected on
Channel 2 within a time period specified by this 12-bit register,
the interrupt request line (
IRQ
) will be activated. T he maximum
time-out period is 0.15 second - see
Zero Crossing Detection
.
Sag line Cycle register. T his 8-bit register specifies the number
of consecutive line cycles the signal on Channel 2 must be below
SAGLVL before the
SAG
output is activated - see
Voltage Sag
Detection
Sag Voltage Level. An 8-bit write to this register determines at
what peak signal level on Channel 2 the SAG pin will become
active. T he signal must remain low for the number of cycles
specified in the SAGCYC register before the SAG pin is
activated—see
Line Voltage Sag Detection
.
Channel 1 Peak Level threshold (current channel). T his register
sets the level of the current peak detection. If the channel 1 input
exceeds this level, the PK I flag in the status register is set.
11h
A POS
R /W
16 bits
0h
12h
W G AIN
R /W
12 bits
0h
13h
W D IV
R /W
8 bits
0h
14h
C F N U M
R /W
12 bits
3F h
15h
C F D E N
R /W
12 bits
3F h
16h
17h
18h
19h
1Ah
IR M S
V R M S
IR M SOS
V R M SOS
V AG AIN
R
R
R /W
R /W
R /W
24 bits
24 bits
12 bits
12 bits
12 bits
0h
0h
0h
0h
0h
1Bh
V AD IV
R /W
8 bits
0h
1C h
L IN E C Y C
R /W
15 bits
F F F h
1D h
Z X T OU T
R /W
12 bits
F F F h
1E h
SA G C Y C
R /W
8 bits
F F h
1F h
SA G L V L
R /W
8 bits
0h
20h
IPK L V L
R /W
8 bits
F F h
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