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參數(shù)資料
| 型號： | ADE7753 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Active and Apparent Energy Metering IC with di/dt sensor interface |
| 中文描述： | 主動與迪視電能計量IC / dt的傳感器接口 |
| 文件頁數(shù)： | 13/38頁 |
| 文件大?。?/td> | 449K |
| 代理商： | ADE7753 |
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ADE7753
–13–
REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
ADE 7753 INT E RRUPT S
ADE7753 Interrupts are managed through the Interrupt
Status register (ST AT US[15:0]) and the Interrupt Enable
register (IRQEN[15:0]). When an interrupt event occurs in
the ADE7753, the corresponding flag in the Status register
is set to a logic one - see Interrupt Status register. If the enable
bit for this interrupt in the Interrupt Enable register is logic
one, then the
IRQ
logic output goes active low. T he flag bits
in the Status register are set irrespective of the state of the
enable bits.
In order to determine the source of the interrupt, the system
master (MC U) should perform a read from the Status
register with reset (RST ST AT US[15:0]). T his is achieved
by carrying out a read from address 0Ch. T he
IRQ
output will
go logic high on completion of the Interrupt Status register
T hus, for example, the nominal maximum code from the
channel 1 ADC with a full scale signal is 2851ECh —see
Channel 1 Sampling
. Multiplying by 2 will give 50A3D8h.
T herefore, writing 50h to the IPK LVL register will put the
channel 1 peak detection level at full scale and set the current
peak detection to its least sensitive value.
Writing 00h will put the channel 1 detection level at zero.
T he detection is done when the content of the IPK L VL
register is smaller than the incoming channel 1 sample.
Peak L evel Record
T he ADE7753 records the maximum absolute value reached
by channel 1 and channel 2 in two different registers - IPEAK
and VPEAK respectively. VPEAK and IPEAK are 24-bit
unsigned registers. T hese registers are updated each time the
absolute value of the Waveform sample from the correspond-
ing channel is above the value stored in the VPEAK or IPEAK
register. T he contents of the VPEAK register corresponds to
2 times the maximum absolute value observed on the channel
2 input. T he contents of IPEAK represents the max absolute
value observed on the channel 1 input. Reading the
RST VPEAK and RST IPEAK registers will clear their re-
spective contents after the read operation.
IRQ
t
1
Jump to
ISR
Global int.
Mask Set
Clear MCU
int. flag
Read
Status with
Reset (05h)
ISR Action
(Based on Status contents)
ISR Return
Global int. Mask
Reset
t
2
t
3
MCU
int. flag set
Jump to
ISR
MCU Program
Sequence
Figure 15– ADE7753 interrupt management
read command—see
Interrupt timing
. When carrying out a read
with reset, the ADE7753 is designed to ensure that no
interrupt events are missed. If an interrupt event occurs just
as the Status register is being read, the event will not be lost
and the
IRQ
logic output is guaranteed to go high for the
duration of the Interrupt Status register data transfer before
going logic low again to indicate the pending interrupt. See
the next section for a more detailed description.
Using the ADE 7753 Interrupts with an MCU
Shown in Figure 15 is a timing diagram which shows a
suggested implementation of ADE7753 interrupt manage-
ment using an MCU. At time
t
1
the
IRQ
line will go active
low indicating that one or more interrupt events have oc-
curred in the ADE7753. T he
IRQ
logic output should be tied
to a negative edge triggered external interrupt on the MCU.
On detection of the negative edge, the MC U should be
configured to start executing its Interrupt Service Routine
(ISR). On entering the ISR, all interrupts should be disabled
using the global interrupt enable bit. At this point the MCU
external interrupt flag can be cleared in order to capture
interrupt events which occur during the current ISR. When
the MCU interrupt flag is cleared a read from the Status
register with reset is carried out. T his will cause the
IRQ
line
to be reset logic high (
t
2
)—see
Interrupt timing
. T he Status
register contents are used to determine the source of the
interrupt(s) and hence the appropriate action to be taken. If
a subsequent interrupt event occurs during the ISR, that event
will be recorded by the MCU external interrupt flag being set
again (
t
3
). On returning from the ISR, the global interrupt
mask will be cleared (same instruction cycle) and the external
interrupt flag will cause the MCU to jump to its ISR once
again. T his will ensure that the MCU does not miss any
external interrupts.
Interrupt timing
T he
ADE7753 Serial Interface
section should be reviewed first
before reviewing the interrupt timing. As previously de-
CS
SCLK
DIN
t
1
t
11
t
11
t
9
DB7
DOUT
DB0
DB0 DB7
0
0
0
Read Status Register Command
0
1
0
0
1
IRQ
Status Register Contents
Figure 16– ADE7753 interrupt timing
相關(guān)PDF資料 |
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| ADE7753ARS | Active and Apparent Energy Metering IC with di/dt sensor interface |
| ADE7753ARSRL | Active and Apparent Energy Metering IC with di/dt sensor interface |
| ADE7754 | ADE7754 |
| ADE7754AR | ADE7754 |
| ADE7754ARRL | ADE7754 |
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| ADE7753_10 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Single-Phase Multifunction Metering IC with di/dt Sensor Interface |
| ADE7753ARS | 制造商:Analog Devices 功能描述:Single Phase Multifunction Metering IC 20-Pin SSOP 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:IC SEMICONDUTOR ((NS)) |
| ADE7753ARSRL | 制造商:Analog Devices 功能描述:Single Phase Multifunction Metering IC 20-Pin SSOP T/R 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| ADE7753ARSZ | 功能描述:IC ENERGY METERING 1PHASE 20SSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 能量測量 系列:- 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:2,500 系列:* |
| ADE7753ARSZ | 制造商:Analog Devices 功能描述:ENERGY METERING IC |
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