ADE7753
A ddress Name
–30–
REV. PrF 10/02
PRELIMINARY TECHNICAL DATA
ADE 7753 RE GIST E R LIST
Default
Description
R/W
# of Bits
01h
W A V E F OR M R
24 bits
0h
T he Waveform register is a read-only register. T his register
contains the sampled waveform data from either Channel 1,
Channel 2 or the Active Power signal. T he data source and the
length of the waveform registers are selected by data bits 14 and
13 in the Mode Register - see
Channel 1 & 2 Sampling
.
T he Active Energy register. Active Power is accumulated
(Integrated) over time in this 24-bit, read-only register. T he
energy register can hold a minimum of 6 seconds of Active
Energy information with full scale analog inputs before it
overflows - see
Energy Calculation
.
Same as the Active Energy register except that the register is
reset to zero following a read operation
Line Accumulation Active Energy register. T he instantaneous
active power is accumulated in this read-only register over the
LINCY C number of half line cycles.
Apparent Energy register. Apparent power is accumulated over
time in this read-only register.
Same as the VAENERGY register except that the register is reset
to zero following a read operation.
Apparent Energy register. T he instantaneous real power is
accumulated in this read-only register over the LINECY C
number of half line cycles
Reactive Energy register. T he instantaneous reactive power is
accumulated in this read-only register over the LINECY C
number of half line cycles.
T he Mode register. T his is a 16-bit register through which most
of the ADE7753 functionality is accessed. Signal sample rates,
filter enabling and calibration modes are selected by writing to
this register. T he contents may be read at any time—see
Mode
Register
.
Interrupt Enable register. ADE7753 interrupts may be
deactivated at any time by setting the corresponding bit in this 8-
bit Enable register to logic zero. T he Status register will
continue to register an interrupt event even if disabled. However,
the
IRQ
output will not be activated—see
ADE7753 Interrupts
.
T he Interrupt Status register. T his is an 8-bit read-only register.
T he Status Register contains information regarding the source of
ADE7753 interrupts - see
ADE7753 Interrupts
.
Same as the Interrupt Status register except that the register
contents are reset to zero (all flags cleared) after a read
operation.
Channel 1 Offset Adjust. Bit 6 is not used. Writing to bits 0 to 5
allows offsets on Channel 1 to be removed – see
Analog Inputs
and CH1OS Register
. Writing a logic one to the MSB of this
register enables the digital integrator on Channel 1, a zero
disables the integrator. T he default value of this bit is zero.
Channel 2 Offset Adjust. Bit 6 and 7 not used. Writing to bits 0
to 5 of this register allows any offsets on Channel 2 to be
removed - see
Analog Inputs
.
PGA Gain Adjust. T his 8-bit register is used to adjust the gain
selection for the PGA in Channel 1 and 2 - see
Analog Inputs
.
02h
AE N E R G Y
R
24 bits
0h
03h
R AE NE R G Y
R
24 bits
0h
04h
L AE N E R G Y
R
24 bits
0h
05h
V AE NE R G Y
R
24 bits
0h
06h
R V AE NE R G Y R
24 bits
0h
07h
L V AE NE R G Y R
24 bits
0h
08h LVARENERGY R
24 bits
0h
09h
M OD E
R /W
16 bits
000C h
0Ah
IR QE N
R /W
16 bits
40h
0Bh
ST A T U S
R
16 bits
0h
0C h
R ST ST A T U S R
16 bits
0h
0D h
C H 1OS
R /W
8 bits
00h
0E h
C H 2OS
R /W
8 bits
0h
0F h
G AIN
R /W
8 bits
0h