I2
參數(shù)資料
型號： ADAU1401AWBSTZ
廠商： Analog Devices Inc
文件頁數(shù)： 40/52頁
文件大?。?/td> 0K
描述： IC AUDIO PROC 28/56BIT 48LQFP
標準包裝： 1
系列： SigmaDSP®
類型： 音頻處理器
應(yīng)用： 監(jiān)控器，電視
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 托盤
ADAU1401A
Rev. A | Page 45 of 52
clock polarity and data input modes. The valid data formats are
I2S, left-justified, right-justified (24-/20-/18-/16-bit), and 8-channel
TDM. In all modes except for the right-justified modes, the serial
port accepts an arbitrary number of bits up to a limit of 24. Extra
bits do not cause an error, but are truncated internally. Proper
operation of the right-justified modes requires that there be exactly
64 BCLKs per audio frame. The TDM data is input on SDATA_IN0.
The LRCLK in TDM mode can be input to the ADAU1401A
either as a 50/50 duty cycle clock or as a bit-wide pulse.
In TDM mode, the ADAU1401A can be a master for 48 kHz
and 96 kHz data, but not for 192 kHz data. Table 64 lists the
modes in which the serial output port can function.
Table 64. Serial Output Port Master/Slave Mode Capabilities
fS
2-Channel Modes
(I2S, Left Justified,
Right Justified)
8-Channel TDM
48 kHz
Master and slave
96 kHz
Master and slave
192 kHz
Master and slave
Slave only
The serial input and output control registers allow the user to
control clock polarities, clock frequencies, clock types, and data
format. In all modes except for the right-justified modes (MSB
delayed by 8, 12, or 16 bits), the serial port accepts an arbitrary
number of bits up to a limit of 24. Extra bits do not cause an error,
but are truncated internally. Proper operation of the right-justified
modes requires the LSB to align with the edge of the LRCLK.
The default settings of all serial port control registers correspond
to 2-channel I2S mode. All register settings apply to both master
and slave modes unless otherwise noted.
The function of each multipurpose pin in serial data port mode
is shown in Table 65. Pin MP0 to Pin MP5 support digital data
input to the ADAU1401A, and Pin MP6 to Pin MP11 handle digital
data output from the DSP. The configuration of the serial data
input port is set in the serial input control register (see Table 51),
and the configuration of the corresponding output port is con-
trolled with the serial output control register (see Table 49). The
clocks of the input port function only as slaves, whereas the
output port clocks can be set to function as either masters or
slaves. The MP4 (INPUT_LRCLK) and MP5 (INPUT_BCLK) pins
are used to clock the SDATA_INx (MP0 to MP3) signals, and the
MP10 (OUTPUT_LRCLK) and MP11 (OUTPUT_BCLK) pins
are used to clock the SDATA_OUTx (MP6 to MP9) signals.
If an external ADC is connected as a slave to the ADAU1401A,
use both the input and output port clocks. The MP10 (OUTPUT_
LRCLK) and MP11 (OUTPUT_BCLK) pins must be set to master
mode and be connected externally to the MP4 (INPUT_LRCLK)
and MP5 (INPUT_BCLK) pins, as well as to the external ADC
clock input pins. The data is output from the external ADC into
the SigmaDSP on the MP0, MP1, MP2, or MP3 (SDATA_INx) pin.
Connections to an external DAC are handled exclusively by the
output port pins. The MP10 (OUTPUT_LRCLK) and MP11
(OUTPUT_BCLK) pins can be set to function as either masters
or slaves, and the MP6 to MP9 (SDATA_OUTx) pins are used
to output data from the SigmaDSP to the external DAC.
Table 66 describes the proper configurations for standard audio
data formats.
Table 65. Multipurpose Pin Serial Data Port Functions
Multipurpose Pin
Function
MP0
SDATA_IN0/TDM_IN
MP1
SDATA_IN1
MP2
SDATA_IN2
MP3
SDATA_IN3
MP4
INPUT_LRCLK (slave only)
MP5
INPUT_BCLK (slave only)
MP6
SDATA_OUT0/TDM_OUT
MP7
SDATA_OUT1
MP8
SDATA_OUT2
MP9
SDATA_OUT3
MP10
OUTPUT_LRCLK (master or slave)
MP11
OUTPUT_BCLK (master or slave)
Table 66. Data Format Configurations
Format
LRCLK Polarity
LRCLK
Type
BCLK Polarity
MSB Position
I2S (see Figure 32)
Frame begins on falling edge
Clock
Data changes on falling edge
Delayed from LRCLK edge
by 1 BCLK
Left-Justified (see Figure 33)
Frame begins on rising edge
Clock
Data changes on falling edge
Aligned with LRCLK edge
Right-Justified (see Figure 34)
Frame begins on rising edge
Clock
Data changes on falling edge
Delayed from LRCLK edge
by 8, 12, or 16 BCLKs
TDM with Clock (see Figure 35)
Frame begins on falling edge
Clock
Data changes on falling edge
Delayed from start of word
clock by 1 BCLK
TDM with Pulse (see Figure 36)
Frame begins on rising edge
Pulse
Data changes on falling edge
Delayed from start of word
clock by 1 BCLK
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ADAU1401AWBSTZ-RL 功能描述:IC AUDIO PROC 28/56BIT 48LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標準包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6
ADAU1401YSTZ 功能描述:IC AUDIO PROC 28/56BIT 48LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標準包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6
ADAU1401YSTZ-RL 功能描述:IC AUDIO PROC 28/56BIT 48LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標準包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6
ADAU1421YSTZ 制造商:Analog Devices 功能描述:
ADAU1421YSTZ-REEL 制造商:Analog Devices 功能描述:
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