I2C PORT The ADAU1401A support" />
參數(shù)資料
型號： ADAU1401AWBSTZ
廠商： Analog Devices Inc
文件頁數(shù)： 16/52頁
文件大小： 0K
描述： IC AUDIO PROC 28/56BIT 48LQFP
標(biāo)準(zhǔn)包裝： 1
系列： SigmaDSP®
類型： 音頻處理器
應(yīng)用： 監(jiān)控器，電視
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 托盤
ADAU1401A
Rev. A | Page 23 of 52
I2C PORT
The ADAU1401A supports a 2-wire serial (I2C-compatible)
microprocessor bus driving multiple peripherals. Two pins—
serial data (SDA) and serial clock (SCL)—carry information
between the ADAU1401A and the system I2C master controller.
In I2C mode, the ADAU1401A is always a slave on the bus,
meaning it cannot initiate a data transfer. Each slave device is
recognized by a unique address. The address byte format is
shown in Table 16. The ADAU1401A slave addresses are set
with the ADDR0 and ADDR1 pins. The address resides in the
first seven bits of the I2C write. The LSB of this byte sets either a
read or write operation. Logic Level 1 corresponds to a read
operation, and Logic Level 0 corresponds to a write operation.
Bit 5 and Bit 6 of the address are set by tying the ADDRx pins of
the ADAU1401A to Logic Level 0 or Logic Level 1. The full byte
addresses, including the pin settings and read/write (R/W) bit,
are shown in
.
Burst mode addressing, where the subaddresses are automati-
cally incremented at word boundaries, can be used for writing
large amounts of data to contiguous memory locations. This
increment happens automatically after a single-word write unless a
stop condition is encountered. The registers and RAMs in the
ADAU1401A range in width from one to five bytes; therefore, the
auto-increment feature knows the mapping between subaddresses
and the word length of the destination register (or memory
location). A data transfer is always terminated by a stop condition.
Both SDA and SCL should have 2.2 kΩ pull-up resistors on the
lines connected to them. The voltage on these signal lines should
not be more than IOVDD (3.3 V).
Table 16. ADAU1401A I2C Address Byte Format
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
0
1
0
1
ADDR1
ADDR0
R/W
Table 17. ADAU1401A I2C Addresses
ADDR1
ADDR0
R/W
Slave Address
0
0x68
0
1
0x69
0
1
0
0x6A
0
1
0x6B
1
0
0x6C
1
0
1
0x6D
1
0
0x6E
1
0x6F
Addressing
Initially, each device on the I2C bus is in an idle state monitoring
the SDA and SCL lines for a start condition and the proper address.
The I2C master initiates a data transfer by establishing a start
condition, defined by a high-to-low transition on SDA while
SCL remains high. This indicates that an address or an address
and a data stream follow. All devices on the bus respond to the
start condition and shift the next eight bits (the 7-bit address
plus the R/W bit) MSB first. The device that recognizes the
transmitted address responds by pulling the data line low
during the ninth clock pulse. This ninth bit is known as an
acknowledge bit. All other devices withdraw from the bus at
this point and return to the idle condition. The R/W bit
determines the direction of the data. A Logic 0 on the LSB of
the first byte means that the master writes information to the
peripheral, whereas a Logic 1 means that the master reads
information from the peripheral after writing the subaddress
and repeating the start address. A data transfer takes place until
a stop condition is encountered. A stop condition occurs when
SDA transitions from low to high while SCL is held high.
shows the timing of an I2C write, and
shows the timing
of an I2C read.
Stop and start conditions can be detected at any stage during the
data transfer. If these conditions are asserted out of sequence
with normal read and write operations, the ADAU1401A
immediately jumps to the idle condition. During a given SCL
high period, the user should only issue one start condition, one
stop condition, or a single stop condition followed by a single
start condition. If an invalid subaddress is issued by the user,
the ADAU1401A does not issue an acknowledge and returns to
the idle condition. If the user exceeds the highest subaddress
while in auto-increment mode, one of two actions is taken. In
read mode, the ADAU1401A outputs the highest subaddress
register contents until the master device issues a no acknowledge,
indicating the end of a read. A no-acknowledge condition is
where the SDA line is not pulled low on the ninth clock pulse
on SCL. On the other hand, if the highest subaddress location is
reached while in write mode, the data for the invalid byte is not
loaded into any subaddress register, a no acknowledge is issued
by the ADAU1401A, and the part returns to the idle condition.
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ADAU1401YSTZ 功能描述:IC AUDIO PROC 28/56BIT 48LQFP RoHS:是 類別:集成電路 (IC) >> 線性 - 音頻處理 系列:SigmaDSP® 其它有關(guān)文件:STA321 View All Specifications 標(biāo)準(zhǔn)包裝:1 系列:Sound Terminal™ 類型:音頻處理器 應(yīng)用:數(shù)字音頻 安裝類型:表面貼裝 封裝/外殼:64-LQFP 裸露焊盤 供應(yīng)商設(shè)備封裝:64-LQFP EP（10x10） 包裝:Digi-Reel® 其它名稱:497-11050-6
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