參數(shù)資料
型號(hào)： AD9991
廠商： Analog Devices, Inc.
英文描述： 10-Bit CCD Signal Processor with Precision Timing Generator
中文描述： 10位CCD信號(hào)處理器與精密時(shí)序發(fā)生器
文件頁(yè)數(shù)： 57/60頁(yè)
文件大小： 826K
代理商： AD9991
AD9991
–57–
Table L. Field 3 Register Map (continued)
Data Bit Default
Address Content Value Register Name Description
E9 [3:0] 0 VSEQSEL4_3 Selected V-Sequence for Region 4.
[4] 0 SWEEP4_3 Select Sweep Region for Region 4. 0 = No Sweep, 1 = Sweep.
[5] 0 MULTI4_3 Select Multiplier Region for Region 4. 0 = No Multiplier, 1 = Multiplier.
[9:6] 0 VSEQSEL5_3 Selected V-Sequence for Region 5.
[10] 0 SWEEP5_3 Select Sweep Region for Region 5. 0 = No Sweep, 1 = Sweep.
[11] 0 MULTI5_3 Select Multiplier Region for Region 5. 0 = No Multiplier, 1 = Multiplier.
[15:12] 0 VSEQSEL6_3 Selected V-Sequence for Region 6.
[16] 0 SWEEP6_3 Select Sweep Region for Region 6. 0 = No Sweep, 1 = Sweep.
[17] 0 MULTI6_3 Select Multiplier Region for Region 6. 0 = No Multiplier, 1 = Multiplier.
[23:18] UNUSED Unused.
EA [11:0] 0 SCP1_3 V-Sequence Change Position #1 for Field 3.
[23:12] 0 SCP2_3 V-Sequence Change Position #2 for Field 3.
EB [11:0] 0 SCP3_3 V-Sequence Change Position #3 for Field 3.
[23:12] 0 SCP4_3 V-Sequence Change Position #4 for Field 3.
EC [11:0] 0 VDLEN_3 VD Field Length (Number of Lines) for Field 3.
[23:12] 0 HDLAST_3 HD Line Length (Number of Pixels) for Last Line in Field 3.
ED [3:0] 0 VPATSECOND_3 Selected Second V-Pattern Group for VSG Active Line.
[9:4] 0 SGMASK_3 Masking of VSG Outputs during VSG Active Line.
[21:10] 0 SGPATSEL_3 Selection of VSG Patterns for Each VSG Output.
EE [11:0] 0 SGLINE1_3 VSG Active Line 1.
[23:12] 0 SGLINE2_3 VSG Active Line 2 (if no Second Line Needed, Set to Same as Line 1 or Max).
EF [11:0] 0 SCP5_3 V-Sequence Change Position #5 for Field 3.
[23:12] 0 SCP6_3 V-Sequence Change Position #6 for Field 3.
Table LI. Field 4 Register Map
Data Bit Default
Address Content Value Register Name Description
F0 [3:0] 0 VSEQSEL0_4 Selected V-Sequence for Region 0.
[4] 0 SWEEP0_4 Select Sweep Region for Region 0. 0 = No Sweep, 1 = Sweep.
[5] 0 MULTI0_4 Select Multiplier Region for Region 0. 0 = No Multiplier, 1 = Multiplier.
[9:6] 0 VSEQSEL1_4 Selected V-Sequence for Region 1.
[10] 0 SWEEP1_4 Select Sweep Region for Region 1. 0 = No Sweep, 1 = Sweep.
[11] 0 MULTI1_4 Select Multiplier Region for Region 1. 0 = No Multiplier, 1 = Multiplier.
[15:12] 0 VSEQSEL2_4 Selected V-Sequence for Region 2.
[16] 0 SWEEP2_4 Select Sweep Region for Region 2. 0 = No Sweep, 1 = Sweep.
[17] 0 MULTI2_4 Select Multiplier Region for Region 2. 0 = No Multiplier, 1 = Multiplier.
[21:18] 0 VSEQSEL3_4 Selected V-Sequence for Region 3.
[22] 0 SWEEP3_4 Select Sweep Region for Region 3. 0 = No Sweep, 1 = Sweep.
[23] 0 MULTI3_4 Select Multiplier Region for Region 3. 0 = No Multiplier, 1 = Multiplier.
F1 [3:0] 0 VSEQSEL4_4 Selected V-Sequence for Region 4.
[4] 0 SWEEP4_4 Select Sweep Region for Region 4. 0 = No Sweep, 1 = Sweep.
[5] 0 MULTI4_4 Select Multiplier Region for Region 4. 0 = No Multiplier, 1 = Multiplier.
[9:6] 0 VSEQSEL5_4 Selected V-Sequence for Region 5.
[10] 0 SWEEP5_4 Select Sweep Region for Region 5. 0 = No Sweep, 1 = Sweep.
[11] 0 MULTI5_4 Select Multiplier Region for Region 5. 0 = No Multiplier, 1 = Multiplier..
[15:12] 0 VSEQSEL6_4 Selected V-Sequence for Region 6.
[16] 0 SWEEP6_4 Select Sweep Region for Region 6. 0 = No Sweep, 1 = Sweep.
[17] 0 MULTI6_4 Select Multiplier Region for Region 6. 0 = No Multiplier, 1 = Multiplier.
[23:18] UNUSED Unused.
F2 [11:0] 0 SCP1_4 V-Sequence Change Position #1 for Field 4.
[23:12] 0 SCP2_4 V-Sequence Change Position #2 for Field 4.
F3 [11:0] 0 SCP3_4 V-Sequence Change Position #3 for Field 4.
[23:12] 0 SCP4_4 V-Sequence Change Position #4 for Field 4.
REV. 0
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AD9992 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit CCD Signal Processor with Precision Timing Generator
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