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| 型號(hào)： | AD9991 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 10-Bit CCD Signal Processor with Precision Timing Generator |
| 中文描述： | 10位CCD信號(hào)處理器與精密時(shí)序發(fā)生器 |
| 文件頁數(shù)： | 18/60頁 |
| 文件大?。?/td> | 826K |
| 代理商： | AD9991 |
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AD9991
–18–
Vertical Sequences (VSEQ)
The vertical sequences are created by selecting one of the 10
V-pattern groups and adding repeats, start position, and horizon-
tal clamping, and blanking information. Up to 10 V-sequences
can be programmed, each using the registers shown in Table VI.
Figure 17 shows how the different registers are used to generate
each V-sequence.
The VPATSEL register selects which V-pattern group will be
used in a given V-sequence. The basic V-pattern group can have
repetitions added, for high speed line shifts or line binning, by
using the VPATREPO and VPATREPE registers. Generally, the
same number of repetitions are programmed into both registers,
but if a different number of repetitions is required on odd and
even lines, separate values may be used for each register (see
the V-Sequence Line Alternation section). The VPATSTART
register specifies where in the line the V-pattern group will start.
The VMASK register is used in conjunction with the FREEZE/
RESUME registers to enable optional masking of the V-outputs.
Either or both of the FREEZE1/RESUME1 and FREEZE2/
RESUME2 registers can be enabled.
The line length (in pixels) is programmable using the HDLEN
registers. Each V-sequence can have a different line length to
accommodate various image readout techniques. The maximum
number of pixels per line is 4096. Note that the last line of the
field is separately programmable using the HDLAST register
located in the Field register section.
Table VI. V-Sequence Registers (see Tables III and IV for HBLK, CLPOB, PBLK Registers)
Register Length Range Description
VPATSEL 4b 0–9 V-Pattern Group # Selected V-Pattern Group for Each V-Sequence.
VMASK 2b 0–3 Mask Mode Enables the Masking of V1–V6 Outputs at the Locations Specified by
the FREEZE/RESUME Registers. 0 = No Mask, 1 = Enable
FREEZE1/RESUME1, 2 = Enable FREEZE2/RESUME2, 3 = Enable
both 1 and 2.
VPATREPO 12b 0–4095 # of Repeats Number of Repetitions for the V-Pattern Group for Odd Lines.
If no odd/even alternation is required, set equal to VPATREPE.
VPATREPE 12b 0–4095 # of Repeats Number of Repetitions for the V-Pattern Group for Even Lines.
If no odd/even alternation is required, set equal to VPATREPO.
VPATSTART 12b 0–4095 Pixel Location Start Position for the Selected V-Pattern Group.
HDLEN 12b 0–4095 # of Pixels HD Line Length for Lines in Each V-Sequence.
VPAT REP 3
HD
V1–V6
PROGRAMMABLE SETTINGS FOR EACH V-SEQUENCE:
1. START POSITION IN THE LINE OF SELECTED V-PATTERN GROUP
2. HD LINE LENGTH
3. V-PATTERN SELECT (VPATSEL) TO SELECT ANY V-PATTERN GROUP
4. NUMBER OF REPETITIONS OF THE V-PATTERN GROUP (IF NEEDED)
5. START POLARITY AND TOGGLE POSITIONS FOR CLPOB AND PBLK SIGNALS
6. MASKING POLARITY AND TOGGLE POSITIONS FOR HBLK SIGNAL
V-PATTERN GROUP
1
3
CLPOB
PBLK
HBLK
2
4
4
VPAT REP 2
5
6
Figure 17. V-Sequence Programmability
REV. 0
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| AD9992 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit CCD Signal Processor with Precision Timing Generator |
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