參數(shù)資料
型號: AD9991
廠商: Analog Devices, Inc.
英文描述: 10-Bit CCD Signal Processor with Precision Timing Generator
中文描述: 10位CCD信號處理器與精密時序發(fā)生器
文件頁數(shù): 44/60頁
文件大?。?/td> 826K
代理商: AD9991
AD9991
–44–
Table XXVII. V-Pattern Group 1 (VPAT1) Register Map (continued)
Data Bit Default
Address Content Value Register Name Description
13 [11:0] 0 V5TOG1_1 V5 Toggle Position 1
[23:12] 0 V5TOG2_1 V5 Toggle Position 2
14 [11:0] 0 V5TOG3_1 V5 Toggle Position 3
[23:12] 0 V6TOG1_1 V6 Toggle Position 1
15 [11:0] 0 V6TOG2_1 V6 Toggle Position 2
[23:12] 0 V6TOG3_1 V6 Toggle Position 3
16 [11:0] 0 FREEZE1_1 V1–V6 Freeze Position 1
[23:12] 0 RESUME1_1 V1–V6 Resume Position 1
17 [11:0] 0 FREEZE2_1 V1–V6 Freeze Position 2
[23:12] 0 RESUME2_1 V1–V6 Resume Position 2
Table XXVIII. V-Pattern Group 2 (VPAT2) Register Map
Data Bit Default
Address Content Value Register Name Description
18 [5:0] 0 VPOL_2 VPAT2 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5].
[11:6] 0 UNUSED Unused.
[23:12] 0 VPATLEN_2 Total Length of VPAT2. Note: If using VPAT2 as a second V-sequence in
the VSG active line, this value is the start position for second V-sequence.
19 [11:0] 0 V1TOG1_2 V1 Toggle Position 1
[23:12] 0 V1TOG2_2 V1 Toggle Position 2
1A [11:0] 0 V1TOG3_2 V1 Toggle Position 3
[23:12] 0 V2TOG1_2 V2 Toggle Position 1
1B [11:0] 0 V2TOG2_2 V2 Toggle Position 2
[23:12] 0 V2TOG3_2 V2 Toggle Position 3
1C [11:0] 0 V3TOG1_2 V3 Toggle Position 1
[23:12] 0 V3TOG2_2 V3 Toggle Position 2
1D [11:0] 0 V3TOG3_2 V3Toggle Position 3
[23:12] 0 V4TOG1_2 V4 Toggle Position 1
1E [11:0] 0 V4TOG2_2 V4 Toggle Position 2
[23:12] 0 V4TOG3_2 V4 Toggle Position 3
1F [11:0] 0 V5TOG1_2 V5 Toggle Position 1
[23:12] 0 V5TOG2_2 V5 Toggle Position 2
20 [11:0] 0 V5TOG3_2 V5 Toggle Position 3
[23:12] 0 V6TOG1_2 V6 Toggle Position 1
21 [11:0] 0 V6TOG2_2 V6 Toggle Position 2
[23:12] 0 V6TOG3_2 V6 Toggle Position 3
22 [11:0] 0 FREEZE1_2 V1–V6 Freeze Position 1
[23:12] 0 RESUME1_2 V1–V6 Resume Position 1
23 [11:0] 0 FREEZE2_2 V1–V6 Freeze Position 2
[23:12] 0 RESUME2_2 V1–V6 Resume Position 2
Table XXIX. V-Pattern Group 3 (VPAT3) Register Map
Data Bit Default
Address Content Value Register Name Description
24 [5:0] 0 VPOL_3 VPAT3 Start Polarity. V1[0]. V2[1]. V3[2]. V4[3]. V5[4]. V6[5].
[11:6] 0 UNUSED Unused.
[23:12] 0 VPATLEN_3 Total Length of VPAT3. Note: If using VPAT3 as a second V-sequence in
the VSG active line, this value is the start position for second V-sequence.
25 [11:0] 0 V1TOG1_3 V1 Toggle Position 1
[23:12] 0 V1TOG2_3 V1 Toggle Position 2
REV. 0
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AD9992 12-Bit CCD Signal Processor with Precision Timing Generator
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AD9992 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit CCD Signal Processor with Precision Timing Generator