參數(shù)資料
型號(hào)： AD9957BSVZ
廠商： ANALOG DEVICES INC
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP100
封裝： ROHS COMPLIANT, MS-026AED-HD, TQFP-100
文件頁(yè)數(shù)： 9/60頁(yè)
文件大?。?/td> 840K
代理商： AD9957BSVZ
AD9957
Rev. 0 | Page 9 of 60
Table 3. Pin Function Descriptions
Pin No.
1, 24, 61, 72, 86,
87, 93, 97 to 100
2
3, 6, 89, 92
74 to 77, 83
17, 23, 30, 47, 57,
64
11, 15, 21, 28, 45,
56, 66
4, 5, 73, 78, 79, 82,
85, 88, 96
13, 16, 22, 29, 46,
58, 62, 63, 65
7
Mnemonic
NC
I/O
1
Description
Not Connected. Allow device pin to float.
PLL_LOOP_FILTER
AVDD (1.8V)
AVDD (3.3V)
DVDD (1.8V)
I
I
I
I
PLL-Loop Filter Compensation. See External PLL Loop Filter Components section.
Analog Core VDD. 1.8 V analog supplies.
Analog DAC VDD. 3.3 V analog supplies.
Digital Core VDD. 1.8 V digital supplies.
DVDD_I/O (3.3V)
I
Digital Input/Output VDD. 3.3 V digital supplies.
AGND
I
Analog Ground.
DGND
I
Digital Ground.
SYNC_IN+
I
Synchronization Signal, Digital Input (Rising Edge Active). Synchronization signal from
external master to synchronize internal subclocks. See the Synchronization of Multiple
Devices section.
Synchronization Signal, Digital Input (Falling Edge Active). Synchronization signal from
external master to synchronize internal subclocks. See the Synchronization of Multiple
Devices section.
Synchronization Signal, Digital Output (Rising Edge Active). Synchronization signal from
internal device subclocks to synchronize external slave devices. See the Synchronization
of Multiple Devices section.
Synchronization Signal, Digital Output (Falling Edge Active). Synchronization signal from
internal device subclocks to synchronize external slave devices. See the Synchronization
of Multiple Devices section.
Synchronization Sample Error, Digital Output (Active High). A high on this pin indicates
that the AD9957 did not receive a valid sync signal on SYNC_IN+/SYNC_IN. See the
Synchronization of Multiple Devices section.
Master Reset, Digital Input (Active High). This pin clears all memory elements and sets
registers to default values.
External Power-Down, Digital Input (Active High). A high level on this pin initiates the
currently programmed power-down mode. See the Power-Down section of this
document for further details. If unused, tie to ground.
PLL Lock, Digital Output (Active High). A high on this pin indicates that the clock
multiplier PLL has acquired lock to the reference clock input.
CCI Overflow Digital Output, Active High. A high on this pin indicates a CCI filter overflow.
This pin remains high until the CCI overflow condition is cleared.
Parallel Data Input Bus (Active High). These pins provide the interleaved, 18-bit, digital, I
and Q vectors for the modulator to upconvert.
In Blackfin interface mode, this pin serves as the I-data serial input.
In Blackfin interface mode, this pin serves as the Q-data serial input.
Parallel Data Clock, Digital Output (Clock). See the Signal Processing section for details.
Transmit Enable, Digital Input (Active High). See the Signal Processing section for details.
FS Input. In Blackfin interface mode, this pin serves as the FS input to receive the RFS
output signal from the Blackfin.
RAM Trigger, Digital Input (Active High). This pin provides control for the RAM amplitude
scaling function. When this function is engaged, a high sweeps the amplitude from the
beginning RAM address to the end. A low sweeps the amplitude from the end RAM
address to the beginning. If unused, connect to ground or supply.
Profile Select Pins, Digital Inputs (Active High). These pins select one of eight
phase/frequency profiles for the DDS core (single tone or carrier tone). Changing the state
of one of these pins transfers the current contents of all I/O buffers to the corresponding
registers. State changes should be set up to the SYNC_CLK pin.
Output System Clock/4, Digital Output (Clock). The I/O_UPDATE and PROFILE<2:0> pins
should be set up to the rising edge of this signal.
8
SYNC_IN
I
9
SYNC_OUT+
O
10
SYNC_OUT
O
12
SYNC_SMP_ERR
O
14
MASTER_RESET
I
18
EXT_PWR_DWN
I
19
PLL_LOCK
O
20
CCI_OVFL
O
25 to 27, 31 to 39,
42 to 44, 48 to 50
42
43
40
41
41
D<17:0>
I
SPORT I-DATA
SPORT Q-DATA
PDCLK/TSCLK
TxENABLE
FS
I
I
O
I
I
51
RT
I
52 to 54
PROFILE<2:0>
I
55
SYNC_CLK
O
相關(guān)PDF資料
PDF描述
AD9957BSVZ-REEL 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC
AD9957_07 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC
AD9958BCPZ-REEL7 2-Channel 500 MSPS DDS with 10-Bit DACs
AD9958 2-Channel 500 MSPS DDS with 10-Bit DACs
AD9958BCPZ 2-Channel 500 MSPS DDS with 10-Bit DACs
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9957BSVZ-REEL 功能描述:IC DDS 1GSPS 14BIT IQ 100TQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
AD9957BSVZREEL13 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:1 GSPS Quadrature Digital Upconverter w/18-Bit IQ Data Path and 14-Bit DAC
AD9958 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:2-Channel 500 MSPS DDS with 10-Bit DACs
AD9958 PCB 制造商:Analog Devices 功能描述:EVAL BOARD ((NS))
AD9958/PCB 制造商:Analog Devices 功能描述:Evaluation Board For 2-Channel 500 MSPS DDS With 10-Bit DACs 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:IC 10-BIT DAC DDS
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