參數(shù)資料
型號(hào): AD9957BSVZ
廠商: ANALOG DEVICES INC
元件分類: 通信及網(wǎng)絡(luò)
英文描述: 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC
中文描述: SPECIALTY TELECOM CIRCUIT, PQFP100
封裝: ROHS COMPLIANT, MS-026AED-HD, TQFP-100
文件頁(yè)數(shù): 54/60頁(yè)
文件大?。?/td> 840K
代理商: AD9957BSVZ
AD9957
Multichip Sync Register
Address 0x0A, four bytes are assigned to this register.
Rev. 0 | Page 54 of 60
Table 26. Bit Descriptions for the Multichip Sync Register
Bit(s)
Mnemonic
Description
31:28
Sync Validation
Delay
delayed sync-in signal for the synchronization validation block in the synchronization receiver.
0: synchronization clock receiver disabled (default).
27
Sync Receiver
Enable
1: synchronization clock receiver enabled.
0: synchronization clock generator disabled (default).
26
Sync Generator
Enable
1: synchronization clock generator enabled.
0: synchronization clock generator coincident with the rising edge of the system clock (default).
25
Sync Generator
Polarity
1: synchronization clock generator coincident with the falling edge of the system clock.
24
Not Available
23:18
Sync State Preset
Value
sync pulse.
17:16
Not Available
15:11
Sync Generator
Delay
generator.
10:8
Not Available
7:3
Sync Receiver
Delay
receiver.
2:0
Not Available
Default is 0000b. This 4-bit number sets the timing skew (in ~150 ps increments) between SYSCLK and the
Default is 000000b. This 6-bit number is the state that the internal clock generator assumes when it receives a
Default is 00000b. This 5-bit number sets the output delay (in ~150 ps increments) of the synchronization
Default is 00000b. This 5-bit number sets the delay input delay (in ~150 ps increments) of the synchronization
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