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參數(shù)資料
| 型號： | AD9957BSVZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | ROHS COMPLIANT, MS-026AED-HD, TQFP-100 |
| 文件頁數(shù)： | 28/60頁 |
| 文件大?。?/td> | 840K |
| 代理商： | AD9957BSVZ |
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AD9957
Rev. 0 | Page 28 of 60
RAM
32
10
Q
STATE
MACHINE
SCLK
I/O_RESET
SDIO
CS
RT
END ADDRESS
START ADDRESS
10
10
ADDRESS STEP RATE
16
RAM MODE
3
CLK
BASEBAND DATA CLOCK
I
16
IS
Q
QS
DDS CLOCK
UP/DOWN COUNTER
I CHANNEL
Q CHANNEL
RAM
SEGMENT
REGISTERS
S
A
D
U/D
32
2
(MSBs)
(LSBs)
16
0
NOTES
1. NONESSENTIAL FUNCTIONAL COMPONENTS ARE RENDERED IN GRAY.
Figure 42. RAM Playback to Baseband Data Path
OVERVIEW OF RAM PLAYBACK MODES
The RAM is operational in any one of four different
playback modes.
Ramp-up
Bidirectional ramp
Continuous bidirectional ramp
Continuous recirculate
RAM playback is only functional when the AD9957 is pro-
grammed for either the QDUC or interpolating DAC mode.
The RAM playback mode is selected via the 3-bit RAM
playback mode word located in each of the RAM segment
registers. Thus, the RAM playback mode is segment dependent.
The RAM playback mode bits are detailed in Table 6.
Table 6. RAM Playback Modes
RAM Playback Mode
Bits<2:0>
001
010
011
100
000, 101, 110, 111
RAM Playback Mode
Ramp-up
Bidirectional ramp
Continuous bidirectional ramp
Continuous recirculate
Not Valid
The continuous bidirectional ramp and continuous recirculate
modes are not available when the baseband scaling multipliers
serve as the destination of RAM playback.
RAM Ramp-Up Mode
In ramp-up mode, upon assertion of an I/O update or a state
change on the RT pin, the RAM begins playback operation
using the parameters programmed into the selected RAM
segment register. Data is extracted from RAM over the specified
address range contained in the start address and end address of
the active RAM segment register. The data is delivered at the
appropriate rate and to the destination as specified by the RAM
playback destination bit.
The playback rate is governed by the timer internal to the RAM
state machine and its period (Δt) is determined by the state of the
RAM playback destination bit as detailed in the RAM playback
operation section.
The internal state machine begins extracting data from the
RAM at the start address and continues to extract data until it
reaches the end address. Upon reaching this address, the state
machine halts.
A graphic representation of the ramp-up mode appears in
Figure 43. The upper trace shows the progression of the RAM
address from the start address to the end address for the active
RAM segment register. The address value advances by one with
each timeout of the timer internal to the state machine. The circled
numbers indicate specific events, explained as follows:
Event 1—an I/O update or state transition on the RT pin. This
event initializes the state machine to the start address of the active
RAM segment register.
Event 2—the state machine reaches the end address of the active
RAM segment register and halts.
START ADDRESS
RAM
ADDRESS
END ADDRESS
1
1 PDCLK CYCLE
OR
M DDS CLOCK CYCLES
Δ
t
I/O_UPDATE OR
RT TRANSITION
2
1
0
Figure 43. Ramp-Up Timing Diagram
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AD9957BSVZ-REEL | 功能描述:IC DDS 1GSPS 14BIT IQ 100TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9957BSVZREEL13 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Quadrature Digital Upconverter w/18-Bit IQ Data Path and 14-Bit DAC |
| AD9958 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2-Channel 500 MSPS DDS with 10-Bit DACs |
| AD9958 PCB | 制造商:Analog Devices 功能描述:EVAL BOARD ((NS)) |
| AD9958/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For 2-Channel 500 MSPS DDS With 10-Bit DACs 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:IC 10-BIT DAC DDS |
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