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參數(shù)資料
| 型號： | AD9957BSVZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | ROHS COMPLIANT, MS-026AED-HD, TQFP-100 |
| 文件頁數(shù)： | 20/60頁 |
| 文件大?。?/td> | 840K |
| 代理商： | AD9957BSVZ |
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AD9957
SIGNAL PROCESSING
For a better understanding of the operation of the AD9957, it
is helpful to follow the signal path in quadrature modulation
mode from the parallel data port to the output of the DAC,
examining the function of each block (see Figure 26).
Rev. 0 | Page 20 of 60
The internal system clock (SYSCLK) signal that generates from
the timing source provided to the REF_CLK pins provides all
timing within the AD9957.
PARALLEL DATA CLOCK (PDCLK)
The AD9957 generates a signal on the PDCLK pin, which is a
clock signal that runs at the sample rate of the parallel data port.
PDCLK serves as a data clock for the parallel port in QDUC
and interpolating DAC modes; in BFI mode, it is a bit clock.
Normally, the device uses the rising edges on PDCLK to latch
the user-supplied data into the data port. Alternatively, the
PDCLK invert bit selects the falling edges as the active edges.
Furthermore, the PDCLK enable bit is used to switch off the
PDCLK signal. Even when the output signal is turned off via
the PDCLK enable bit, PDCLK continues to operate internally.
The device uses PDCLK internally to capture parallel data. Note
that PDCLK is Logic 0 when disabled.
In QDUC mode, the AD9957 expects alternating I- and Q-
data-words at the parallel port (see Figure 31). Each active edge
of PDCLK captures one 18-bit word, therefore, there are two
PDCLK cycles per I/Q pair. In BFI mode, the AD9957 expects
two serial bit streams, each segmented into 16-bit words with
PDCLK indicating each new bit. In either case, the output clock
rate is f
PDCLK
as explained in the Input Data Assembler section.
In QDUC applications that require a consistent timing
relationship between the internal SYSCLK signal and the
PDCLK signal, the PDCLK rate control bit is used to slightly
alter the operation of PDCLK. When this bit is set, the PDCLK
rate is reduced by a factor of two. This causes rising edges on
PDCLK to latch incoming I-words and falling edges to latch
incoming Q-words. Again, the edge polarity assignment is
reversible via the PDCLK invert bit.
TRANSMIT ENABLE PIN (TxENABLE)
The AD9957 accepts a user-generated signal applied to the
TxENABLE pin that gates the user supplied data. Polarity of the
TxENABLE pin is set using the TxENABLE invert bit (see the
Register Map section for details). When TxENABLE is true, the
device latches data into the device on the expected edge of
PDCLK (based on the PDCLK invert bit). When TxENABLE
is false, the device ignores the data supplied to the port, even
though the PDCLK may continue to operate. Furthermore,
when the TxENABLE pin is held false, then the device either
forces the 18-bit data-words to Logic 0s, or it retains the last
value present on the data port prior to TxENABLE switching
to the false state (see the data assembler hold last value bit in
the Register Map section).
Alternatively, rather than operating the TxENABLE pin as a
gate for framing bursts of data, it can be driven with a clock
signal operating at the parallel port data rate. When driven by
a clock signal, the transition from the false to true state must
meet the required setup and hold times on each cycle to ensure
proper operation.
In QDUC mode, on the false-to-true edge of TxENABLE, the
device is ready to receive the first I-word. The first I-word is
latched into the device coincident with the active edge of
PDCLK. The next active edge of PDCLK latches in a Q-word,
and so on, until TxENABLE is returned to a static false state.
The user may reverse the ordering of the I- and Q-words via
the Q-First Data Pairing bit. Furthermore, the user must ensure
that an even number of data words are delivered to the device as
it must capture both an I- and a Q-word before the data is
processed along the signal chain.
In interpolating DAC mode, TxENABLE operation is similar to
QDUC mode, but without the need for I/Q data pairing; the
even-number-of-PDCLK-cycles rule does not apply.
In BFI mode, operation of the TxENABLE pin is similar except
that instead of the false-to-true edge marking the first I-word, it
marks the first I and Q bit in a serial frame. The user must ensure
that all 16-bits of a serial frame are delivered because the device
must capture a full 16-bit I- and Q-word before the data is proc-
essed along the signal chain.
The timing relationships between TxENABLE, PDCLK, and
DATA are shown in Figure 30, Figure 31, and Figure 32.
Table 4. Parallel and Serial Data Bus Timing
Symbol
t
DS
t
DH
Definition
Data Setup Time
Data Hold Time
Data Bus Minimum
Parallel/Serial
2 ns
1 ns
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9957BSVZ-REEL | 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC |
| AD9957_07 | 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC |
| AD9958BCPZ-REEL7 | 2-Channel 500 MSPS DDS with 10-Bit DACs |
| AD9958 | 2-Channel 500 MSPS DDS with 10-Bit DACs |
| AD9958BCPZ | 2-Channel 500 MSPS DDS with 10-Bit DACs |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9957BSVZ-REEL | 功能描述:IC DDS 1GSPS 14BIT IQ 100TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9957BSVZREEL13 | 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Quadrature Digital Upconverter w/18-Bit IQ Data Path and 14-Bit DAC |
| AD9958 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2-Channel 500 MSPS DDS with 10-Bit DACs |
| AD9958 PCB | 制造商:Analog Devices 功能描述:EVAL BOARD ((NS)) |
| AD9958/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For 2-Channel 500 MSPS DDS With 10-Bit DACs 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:IC 10-BIT DAC DDS |
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