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參數(shù)資料
| 型號： | AD9954YSV-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | 400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| 中文描述： | DSP-NUM CONTROLLED OSCILLATOR, PQFP48 |
| 封裝： | EXPOSED PAD, PLASTIC, MS-026-ABC, TQFP-48 |
| 文件頁數(shù)： | 6/36頁 |
| 文件大?。?/td> | 1027K |
| 代理商： | AD9954YSV-REEL7 |
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AD9954
Parameter
Maximum Data Valid Time
Wake-Up Time
4
Minimum Reset Pulse Width High
I/O UPDATE, PS0, PS1 to SYNCCLK Setup Time DVDD_I/O = 3.3 V
I/O UPDATE, PS0, PS1 to SYNCCLK Setup Time DVDD_I/O = 3.3 V
I/O UPDATE, PS0, PS1 to SYNCCLK Hold Time
Latency
I/O UPDATE to Frequency Change Prop Delay
I/O UPDATE to Phase Offset Change Prop Delay
I/O UPDATE to Amplitude Change Prop Delay
PS0, PS1 to RAM Driven Frequency Change Prop Delay
PS0, PS1 to RAM Driven Phase Change Prop Delay
PS0 to Linear Frequency Sweep Prop Delay
CMOS LOGIC INPUTS
Logic 1 Voltage @ DVDD_I/O (Pin 43) = 1.8 V
Logic 0 Voltage @ DVDD_I/O (Pin 43) = 1.8 V
Logic 1 Voltage @ DVDD_I/O (Pin 43) = 3.3 V
Logic 0 Voltage @ DVDD_I/O (Pin 43) = 3.3 V
Logic 1 Current
Logic 0 Current
Input Capacitance
CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 1.8 V
Logic 1 Voltage
Logic 0 Voltage
CMOS LOGIC OUTPUTS (1 mA Load) DVDD_I/O = 3.3 V
Logic 1 Voltage
Logic 0 Voltage
POWER CONSUMPTION (AVDD = DVDD = 1.8 V)
Single Tone Mode (Comparator Off)
With RAM or Linear Sweep Enabled
With Comparator Enabled
With RAM and Comparator Enabled
Rapid Power-Down Mode
Full-Sleep Mode
SYNCHRONIZATION FUNCTION
6
Maximum SYNC Clock Rate (DVDD_I/O = 1.8 V)
Maximum SYNC Clock Rate (DVDD_I/O = 3.3 V)
SYNC_CLK Alignment Resolution
7
Rev. 0 | Page 6 of 36
Temp
FULL
FULL
FULL
FULL
FULL
FULL
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
25°C
Test
Level
IV
IV
IV
I
I
I
IV
IV
IV
IV
IV
IV
I
I
I
I
V
I
I
I
I
I
I
I
I
I
I
VI
VI
V
Min
5
4
6
0
24
24
16
28
28
28
1.25
2.2
1.35
2.8
62.5
100
Typ
25
1
3
2
162
175
180
198
150
20
±1
Max
0.6
0.8
12
12
0.4
0.4
171
190
190
220
160
27
Unit
ns
ms
SYSCLK Cycles
5
ns
ns
ns
SYSCLK Cycles
SYSCLK Cycles
SYSCLK Cycles
SYSCLK Cycles
SYSCLK Cycles
SYSCLK Cycles
V
V
V
V
μA
μA
pF
V
V
V
V
mW
mW
mW
mW
mW
mW
MHz
MHz
SYSCLK Cycles
1
To achieve the best possible phase noise, the largest amplitude clock possible should be used. Reducing the clock input amplitude will reduce the phase noise per-
formance of the device.
2
Represents the cycle-to-cycle residual jitter from the comparator alone.
3
Represents the cycle-to-cycle residual jitter from the DDS core driving the comparator.
4
Wake-up time refers to the recovery from analog power-down modes (see section on Power-Down Modes of Operation). The longest time required is for the reference
clock multiplier PLL to relock to the reference. The wake-up time assumes there is no capacitor on DAC_BP and that the recommended PLL loop filter values are used.
5
SYSCLK cycle refers to the actual clock frequency used on-chip by the DDS. If the reference clock multiplier is used to multiply the external reference clock frequency,
the SYSCLK frequency is the external frequency multiplied by the reference clock multiplication factor. If the reference clock multiplier is not used, the SYSCLK fre-
quency is the same as the external reference clock frequency.
6
SYNC_CLK = SYSCLK rate. For SYNC_CLK rates
≥
50 MHz, the high speed sync enable bit, CFR2<11>, should be set.
7
This parameter indicates that the digital synchronization feature cannot overcome phase delays (timing skew) between system clock rising edges. If the system clock
edges are aligned, the synchronization function should not increase the skew between the two edges.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9954YSVZ | 功能描述:IC DDS DAC 14BIT 1.8V 48-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9954YSVZ | 制造商:Analog Devices 功能描述:IC DDS 400MSPS SMD 9954 TQFP48 |
| AD9954YSVZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 14-Bit, 1.8 V CMOS, Direct Digital Synthesizer |
| AD9954YSVZ-REEL7 | 功能描述:IC DDS DAC 14BIT 1.8V 48TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9954YSVZ-REEL71 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 14-Bit, 1.8 V CMOS, Direct Digital Synthesizer |
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