- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373972 > AD9954YSV-REEL7 (ANALOG DEVICES INC) 400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer PDF資料下載
參數(shù)資料
| 型號： | AD9954YSV-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | 400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| 中文描述： | DSP-NUM CONTROLLED OSCILLATOR, PQFP48 |
| 封裝： | EXPOSED PAD, PLASTIC, MS-026-ABC, TQFP-48 |
| 文件頁數(shù)： | 23/36頁 |
| 文件大?。?/td> | 1027K |
| 代理商： | AD9954YSV-REEL7 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁當前第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
AD9954
If the no dwell bit is clear when the RAM address generator
equals the final address, the generator stops incrementing as the
terminal frequency has been reached. The sweep is complete
and does not restart until an I/O UPDATE or change in profile
is detected to enable another sweep from the beginning to the
final RAM address as described above.
Rev. 0 | Page 23 of 36
If the no dwell bit is set when the RAM address generator
equals the final address, after the next ramp rate timer cycle, the
phase accumulator is cleared. The phase accumulator remains
cleared until another sweep is initiated via an I/O UPDATE
input or change in profile.
Another application for ramp-up mode is nonsymmetrical FSK
modulation. With the RAM configured for two segments, using
the Profile<0> bit as the data input allows nonsymmetrical
ramped FSK.
Bidirectional Ramp Mode
Bidirectional ramp mode allows the AD9954 to offer a symmet-
rical sweep between two frequencies using the Profile<0> signal
as the control input. The AD9954 is programmed for bidirec-
tional ramp mode by writing the RAM enable bit true and the
RAM mode control bits of RSCW0 to Logic 010(b). In bidirec-
tional ramp mode, the Profile<1> input is ignored and the Pro-
file<0> input is the ramp direction indicator. In this mode, the
memory is not segmented and uses only a single beginning and
final address. The address registers that affect the control of the
RAM are located in the RSCW associated with Profile 0.
Upon entering this mode (via an I/O UPDATE or changing
Profile<0>), the RAM address generator loads the RAM seg-
ment beginning address bits of RSCW0 and the ramp rate timer
loads the RAM segment address ramp rate bits. The RAM
drives data from the beginning address, and the ramp rate timer
begins to count down to 1. While operating in this mode, tog-
gling the Profile<0> pin does not cause the device to generate
an internal I/O UPDATE. When the Profile<0> pin is acting as
the ramp direction indicator, any transfer of data from the I/O
buffers to the internal registers can only be initiated by a rising
edge on the I/O UPDATE pin.
RAM address control now is a function of the Profile<0> input.
When the Profile<0> bit is a Logic 1, the RAM address genera-
tor increments to the next address when the ramp rate timer
completes a cycle (and reloads to start the timer again). As in
the ramp-up mode, this sequence continues until the RAM
address generator has incremented to an address equal to the
final address as long as the Profile<0> input remains high. If the
Profile<0> input goes low, the RAM address generator immedi-
ately decrements and the ramp rate timer is reloaded. The RAM
address generator will continue to decrement at the ramp rate
period until the RAM address is equal to the beginning address
as long as the Profile<0> input remains low.
The sequence of ramping up and down is controlled via the
Profile<0> input signal for as long as the part is programmed
into this mode. The no dwell bit is a Don’t Care in this mode as
is all data in the RAM segment control words associated with
Profiles 1, 2, and 3. Only the information in the RAM segment
control word for Profile 0 is used to control the RAM in the
bidirectional ramp mode.
Continuous Bidirectional Ramp Mode
Continuous bidirectional ramp mode allows the AD9954 to
offer an automatic symmetrical sweep between two frequencies.
The AD9954 is programmed for continuous bidirectional ramp
mode by writing the RAM enable bit true and the RAM mode
control bits of each profile to be used to Logic 011(b).
Upon entering this mode (via an I/O UPDATE or changing
Profile<1:0>), the RAM address generator loads the RAM seg-
ment beginning address bits of the current RSCW and the ramp
rate timer loads the RAM segment address ramp rate bits. The
RAM drives data from the beginning address, and the ramp rate
timer begins to count down to 1. When the ramp rate timer
completes a cycle, the RAM address generator increments to the
next address, and the timer reloads the ramp rate bits and con-
tinues counting down. This sequence continues until the RAM
address generator has incremented to an address equal to the
RAM segment final address bits of the current RSCW. Upon
reaching this terminal address, the RAM address generator will
decrement in value at the ramp rate until it reaches the RAM
segment beginning address. Upon reaching the beginning ad-
dress, the entire sequence repeats.
The entire sequence repeats for as long as the part is pro-
grammed for this mode. The no dwell bit is a Don’t Care in this
mode. In general, this mode is identical in control to the bidi-
rectional ramp mode except the ramp up and down is automatic
(no external control via the Profile<0> input) and switching
profiles is valid. Once in this mode, the address generator ramps
from the beginning address to the final address, then back to
the beginning address at the rate programmed into the ramp
rate register. This mode enables generation of an automatic saw
tooth sweep characteristic.
Continuous Recirculate Mode
Continuous recirculate mode allows the AD9954 to offer
an automatic, continuous unidirectional sweep between two
frequencies. The AD9954 is programmed for continuous
recirculate mode by writing the RAM enable bit true and the RAM
mode control bits of each profile to be used to Logic 100(b).
Upon entering this mode (via an I/O UPDATE or changing
Profile<1:0>), the RAM address generator loads the RAM seg-
ment beginning address bits of the current RSCW and the ramp
rate timer loads the RAM segment address ramp rate bits. The
RAM drives data from the beginning address, and the ramp rate
timer begins to count down to 1. When the ramp rate timer
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9956 | 2.7 GHz DDS-Based AgileRF |
| AD9956YCPZ-REEL1 | 2.7 GHz DDS-Based AgileRF |
| AD9956YCPZ1 | 2.7 GHz DDS-Based AgileRF |
| AD9957 | 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC |
| AD9957BSVZ | 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9954YSVZ | 功能描述:IC DDS DAC 14BIT 1.8V 48-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9954YSVZ | 制造商:Analog Devices 功能描述:IC DDS 400MSPS SMD 9954 TQFP48 |
| AD9954YSVZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 14-Bit, 1.8 V CMOS, Direct Digital Synthesizer |
| AD9954YSVZ-REEL7 | 功能描述:IC DDS DAC 14BIT 1.8V 48TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9954YSVZ-REEL71 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 14-Bit, 1.8 V CMOS, Direct Digital Synthesizer |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。