- 您現在的位置：買賣IC網 > PDF目錄373972 > AD9954YSV-REEL7 (ANALOG DEVICES INC) 400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer PDF資料下載
參數資料
| 型號： | AD9954YSV-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數字信號處理外設 |
| 英文描述： | 400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| 中文描述： | DSP-NUM CONTROLLED OSCILLATOR, PQFP48 |
| 封裝： | EXPOSED PAD, PLASTIC, MS-026-ABC, TQFP-48 |
| 文件頁數： | 25/36頁 |
| 文件大?。?/td> | 1027K |
| 代理商： | AD9954YSV-REEL7 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁當前第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁
AD9954
Linear Sweep Mode
The AD9954 is placed in linear sweep mode by setting the lin-
ear sweep enable bit CR1<21>. When in linear sweep mode, the
AD9954 output frequency will ramp up from a starting fre-
quency, programmed by FTW0 to a finishing frequency FTW1,
or down from FTW1 to FTW0. The delta frequency tuning
words and the ramp rate word determine the rate at which this
ramping takes place. The linear sweep no-dwell bit CFR1<2>
controls the behavior of the device upon reaching the terminal
frequency. The 32-bit rising delta frequency tuning word
(RDFTW) increments the frequency accumulator when ramp-
ing up from FTW0 to FTW1. The 8-bit rising sweep ramp rate
word (RSRRW) controls the rate at which the frequency accu-
mulator is incremented. The 32-bit falling delta frequency tun-
ing word (FDFTW) decrements the accumulator when ramping
down from FTW1 to FTW0. The 8-bit falling sweep ramp rate
word (FSRRW) determines the rate at which the accumulator is
decremented.
Rev. 0 | Page 25 of 36
The PS<0> pin controls the direction of the sweep, rising to
FTW1 or falling to FTW0. Upon reaching the destination fre-
quency, the AD9954 linear sweep function will either hold at the
destination frequency until the state on the PS<0> pin is
changed or immediately return to the initial frequency, FTW0,
depending on the state of the linear sweep no-dwell bit
CFR1<02>. While operating in linear sweep mode, toggling the
Profile<0> pin does not cause the device to generate an internal
I/O UPDATE. When the PS<0> pin is acting as the sweep direc-
tion indicator, any transfer of data from the I/O buffers to the
internal registers can only be initiated by a rising edge on the
I/O UPDATE pin.
The linear sweep function of the AD9954 requires the lowest
frequency to be loaded into the FTW0 register and the highest
frequency into the FTW1 register. For piece-wise, nonlinear
frequency transitions, it is necessary to reprogram the registers
while the frequency transition is in progress to affect the desired
response. Figure 20 demonstrates a typical frequency ramping
operation. After a reset, the device will initially be in single tone
mode. The programming steps to operate in linear sweep mode
are
0)
Profile inputs at 00.
1)
Set the linear sweep enable bit (CFR1<21> = 1) and
set or clear the linear sweep no-dwell bit (CFR1<2> =
{0,1}) as desired.
2)
Program the rising and falling delta frequency tuning
words and ramp rate values.
3)
Program the lower and higher output frequencies into
the FTW0 and FTW1 registers, respectively.
4)
Apply an I/O UPDATE to move this data into the reg-
isters (the output frequency will be FTW0).
5)
Change the PS<0> input as desired to sweep between
the lower to higher frequency and back.
Figure 20 shows that the device initially powers up in single
tone mode. The profile inputs are low, which places the FTW0
input to the phase accumulator. The user then configures the
device as desired by writing the rising and falling delta
frequency tuning words and ramp rates, as well as the linear
sweep enable bit, via the serial port (Point A in Figure 20). In this
example, the linear sweep no-dwell bit is cleared (CFR1<2> = 0).
General Operation of Linear Sweep Capability
In linear sweep mode, the PS<1> pin must be tied to Logic 0.
With linear sweep mode active, when the PS<0> pin transitions
from low to high, the RDFTW is applied to the input of the
frequency accumulator and the RSRR register is loaded into the
sweep rate timer. The sweep rate timer counts down from an
initial value to one, at which point the frequency accumulator is
allowed to accumulate the input. This accumulation of the
RDFTW at the rate given by the ramp rate (RSRR) continues
until the output of the frequency adder is equal to the FTW1
register value. At this time the accumulation is stopped, causing
the AD9954 to output the frequency given by the FTW1. The
output remains at FTW1 for as long as the PS<0> pin remains
at Logic 1.
When the PS<0> pin transitions from high to low, the
negated FDFTW is applied to the input of the frequency accu-
mulator and the FSRR register is loaded into the sweep rate
timer. Each time the timer counts down to one, the frequency
accumulator is allowed to accumulate the input. This accumula-
tion of the negated FDFTW at the rate given by the ramp rate
(FSRR) continues until the output of the frequency adder is
equal to the FTW0 register value. At this time the accumulation
is stopped, causing the AD9954 to output the frequency given
by the FTW0. The output remains at FTW0 for as long as the
PS<0> pin remains at Logic 0.
相關PDF資料 |
PDF描述 |
|---|---|
| AD9956 | 2.7 GHz DDS-Based AgileRF |
| AD9956YCPZ-REEL1 | 2.7 GHz DDS-Based AgileRF |
| AD9956YCPZ1 | 2.7 GHz DDS-Based AgileRF |
| AD9957 | 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC |
| AD9957BSVZ | 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC |
相關代理商/技術參數 |
參數描述 |
|---|---|
| AD9954YSVZ | 功能描述:IC DDS DAC 14BIT 1.8V 48-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9954YSVZ | 制造商:Analog Devices 功能描述:IC DDS 400MSPS SMD 9954 TQFP48 |
| AD9954YSVZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 14-Bit, 1.8 V CMOS, Direct Digital Synthesizer |
| AD9954YSVZ-REEL7 | 功能描述:IC DDS DAC 14BIT 1.8V 48TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9954YSVZ-REEL71 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 14-Bit, 1.8 V CMOS, Direct Digital Synthesizer |
發(fā)布緊急采購，3分鐘左右您將得到回復。