參數(shù)資料
型號(hào)： AD9954YSV-REEL7
廠商： ANALOG DEVICES INC
元件分類(lèi)： 數(shù)字信號(hào)處理外設(shè)
英文描述： 400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer
中文描述： DSP-NUM CONTROLLED OSCILLATOR, PQFP48
封裝： EXPOSED PAD, PLASTIC, MS-026-ABC, TQFP-48
文件頁(yè)數(shù)： 30/36頁(yè)
文件大?。?/td> 1027K
代理商： AD9954YSV-REEL7
AD9954
Rev. 0 | Page 30 of 36
SYNC_CLK
SYSCLK
A
B
DATA 2
DATA 3
DATA 1
DATA IN
REGISTERS
DATA IN
I/O BUFFERS
DATA 1
DATA 2
DATA 3
I/O UPDATE
THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM THE ASYNCHRONOUSLY LOADED I/O BUFFERS AT POINT B.
0
Figure 24. I/O Synchronization Timing Diagram
Synchronizing Multiple AD9954s
The AD9954 product allows easy synchronization of multiple
AD9954s. There are three modes of synchronization available
to the user: an automatic synchronization mode, a software
controlled manual synchronization mode, and a hardware
controlled manual synchronization mode. In all cases, when a
user wants to synchronize two or more devices, the following
considerations must be observed. First, all units must share a
common clock source. Trace lengths and path impedance of the
clock tree must be designed to keep the phase delay of the dif-
ferent clock branches as closely matched as possible. Second, the
I/O UPDATE signal’s rising edge must be provided synchro-
nously to all devices in the system. Finally, regardless of the
internal synchronization method used, the DVDD_I/O supply
should be set to 3.3 V for all devices that are to be synchronized.
AVDD and DVDD should be left at 1.8 V.
In automatic synchronization mode, one device is chosen as a
master, the other device(s) will be slaved to this master. When
configured in this mode, all the slaves will automatically syn-
chronize their internal clocks to the SYNC_CLK output signal
of the master device. To enter automatic synchronization mode,
set the slave device’s automatic synchronization bit (CFR1<23>
= 1). Connect the SYNC_IN input(s) to the master SYNC_CLK
output. The slave device will continuously update the phase
relationship of its SYNC_CLK until it is in phase with the
SYNC_IN input, which is the SYNC_CLK of the master device.
When attempting to synchronize devices running at SYSCLK
speeds beyond 250 MSPS, the high speed sync enhancement
enable bit should be set (CFR2<11> = 1).
In software manual synchronization mode, the user forces the
device to advance the SYNC_CLK rising edge one SYSCLK
cycle (1/4 SYNC_CLK period). To activate the manual
synchronization mode, set the slave device’s software manual
synchronization bit (CFR1<22> = 1). The bit (CFR1<22>) will be
immediately cleared. To advance the rising edge of the SYNC_CLK
multiple times, this bit will need to be set multiple times.
In hardware manual synchronization mode, the SYNC_IN
input pin is configured such that it will now advance the rising
edge of the SYNC_CLK signal each time the device detects a
rising edge on the SYNC_IN pin. To put the device into hard-
ware manual synchronization mode, set the hardware manual
synchronization bit (CFR2<10> = 1). Unlike the software man-
ual synchronization bit, this bit does not self-clear. Once the
hardware manual synchronization mode is enabled, all rising
edges detected on the SYNC_IN input will cause the device to
advance the rising edge of the SYNC_CLK by one SYSCLK
cycle until this enable bit is cleared (CFR2<10> = 0).
Using a Single Crystal to Drive Multiple AD9954 Clock
Inputs
The AD9954 crystal oscillator output signal is available on the
CRYSTAL OUT pin, enabling one crystal to drive multiple
AD9954s. In order to drive multiple AD9954s with one crystal,
the CRYSTAL OUT pin of the AD9954 using the external crys-
tal should be connected to the REFCLK input of the other
AD9954.
The CRYSTAL OUT pin is static until the CFR2<1> bit is set,
enabling the output. The drive strength of the CRYSTAL OUT
pin is typically very low, so this signal should be buffered prior
to using it to drive any loads.
SERIAL PORT OPERATION
With the AD9954, the instruction byte specifies read/write
operation and register address. Serial operations on the AD9954
occur only at the register level, not the byte level. For the
AD9954, the serial port controller recognizes the instruction
byte register address and automatically generates the proper
register byte address. In addition, the controller expects that all
bytes of that register will be accessed. It is a requirement that all
bytes of a register be accessed during serial I/O operations, with
one exception. The IOSYNC function can be used to abort an
I/O operation, thereby allowing less than all bytes to be ac-
cessed.
There are two phases to a communication cycle with the
AD9954. Phase 1 is the instruction cycle, which is the writing of
an instruction byte into the AD9954, coincident with the first
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