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參數(shù)資料
| 型號： | AD9954YSV-REEL7 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 數(shù)字信號處理外設(shè) |
| 英文描述： | 400 MSPS 14-Bit, 1.8 V CMOS Direct Digital Synthesizer |
| 中文描述： | DSP-NUM CONTROLLED OSCILLATOR, PQFP48 |
| 封裝： | EXPOSED PAD, PLASTIC, MS-026-ABC, TQFP-48 |
| 文件頁數(shù)： | 29/36頁 |
| 文件大?。?/td> | 1027K |
| 代理商： | AD9954YSV-REEL7 |
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AD9954
External Shaped On-Off Keying Mode Operation
Rev. 0 | Page 29 of 36
The external Shaped On-Off Keying mode is enabled by writing
CFR1<25> to a logic 1 AND writing CFR1<24> to a Logic 0.
When configured for external Shaped On-Off Keying, the
content of the ASFR becomes the scale factor for the data path.
The scale factors are synchronized to SYNC_CLK via the I/O
UPDATE functionality.
Synchronization; Register Updates (I/O UPDATE)
Functionality of the SYNC_CLK and I/O UPDATE
Data into the AD9954 is synchronous to the SYNC_CLK signal
(supplied externally to the user on the SYNC_CLK pin). The
I/O UPDATE pin is sampled on the rising edge of the
SYNC_CLK.
Internally, SYSCLK is fed to a divide-by-4 frequency divider to
produce the SYNC_CLK signal. The SYNC_CLK signal is pro-
vided to the user on the SYNC_CLK pin. This enables synchro-
nization of external hardware with the device’s internal clocks.
This is accomplished by forcing any external hardware to obtain
its timing from SYNC_CLK. The I/O UPDATE signal coupled
with SYNC_CLK is used to transfer internal buffer contents
into the control registers of the device. The combination of the
SYNC_CLK and I/O UPDATE pins provide the user with
constant latency relative to SYSCLK and also ensures phase
continuity of the analog output signal when a new tuning word
or phase offset value is asserted. Figure 23 demonstrates an I/O
UPDATE timing cycle and synchronization.
Notes to synchronization logic:
1)
The I/O UPDATE signal is edge detected to generate a
single rising edge clock signal that drives the register bank
flops. The I/O UPDATE signal has no constraints on duty
cycle. The minimum low time on I/O UPDATE is one
SYNC_CLK clock cycle.
2)
The I/O UPDATE pin is set up and held around the rising
edge of SYNC_CLK and has zero hold time and 4 ns setup
time.
0
SYSCLK
SDI
CS
SYNC_CLK
DISABLE
1
0
0
SCLK
TO CORE LOGIC
OSK
D
Q
PROFILE<1:0>
D
Q
I/O UPDATE
D
Q
÷ 4
SYNC_CLK
GATING
EDGE
DETECTION
LOGIC
REGISTER
MEMORY
I/O BUFFER
LATCHES
Figure 23. I/O Synchronization Block Diagram
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9954YSVZ | 功能描述:IC DDS DAC 14BIT 1.8V 48-TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9954YSVZ | 制造商:Analog Devices 功能描述:IC DDS 400MSPS SMD 9954 TQFP48 |
| AD9954YSVZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 14-Bit, 1.8 V CMOS, Direct Digital Synthesizer |
| AD9954YSVZ-REEL7 | 功能描述:IC DDS DAC 14BIT 1.8V 48TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9954YSVZ-REEL71 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MSPS, 14-Bit, 1.8 V CMOS, Direct Digital Synthesizer |
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