參數(shù)資料
型號： AD9895KBC
廠商： ANALOG DEVICES INC
元件分類： 消費家電
英文描述： CCD Signal Processors with Precision Timing⑩ Generator
中文描述： SPECIALTY CONSUMER CIRCUIT, PBGA64
封裝： PLASTIC, CSPBGA-64
文件頁數(shù)： 7/59頁
文件大?。?/td> 599K
代理商： AD9895KBC
REV. A
AD9891/AD9895
–7–
AD9891 PIN CONFIGURATION
A
B
C
D
E
F
G
H
J
K
AD9891
(NoVIEW
1 2 3 4 5 6 7
9 10
8
A1 CORNER
PIN FUNCTION DESCRIPTIONS
1
Pin
Mnemonic Type
2
Description
K9
J9
K10
J10
H10
H9
G10
G9
F10
F9
E10
E9
D9
D10
VSG5
VSG6
VSG7
VSG8
H1
H2
HVDD
HVSS
H3
H4
RGVDD
RGVSS
RG
CLO
DO
DO
DO
DO
DO
DO
P
P
DO
DO
P
P
DO
DO
CCD Sensor Gate Pulse 5
CCD Sensor Gate Pulse 6
CCD Sensor Gate Pulse 7
CCD Sensor Gate Pulse 8
CCD Horizontal Clock 1
CCD Horizontal Clock 2
H1
–
H4 Driver Supply
H1
–
H4 Driver Ground
CCD Horizontal Clock 3
CCD Horizontal Clock 4
RG Driver Supply
RG Driver Ground
CCD Reset Gate Clock
Reference Clock Output for
Crystal
Reference Clock Input
Analog Supply for Timing Core
Analog Ground for Timing
Core
Analog Supply for AFE
Analog Ground for AFE
Analog Circuit Bypass
Analog Circuit Bypass
CCD Signal Input
Analog Circuit Bypass
Analog Supply for AFE
Analog Ground for AFE
Voltage Reference Bottom
Bypass
Voltage Reference Top Bypass
3-Wire Serial Load Pulse
3-Wire Serial Data Input
3-Wire Serial Clock
Mechanical Shutter Pulse
Strobe Pulse
Digital Ground
Digital Supply for VSG,
V1
–
V4, HD, VD, MSHUT,
STROBE, and Serial Interface
C10
B10
C9
CLI
TCVDD
TCVSS
DI
P
P
A10
B9
A9
B8
A8
A7
B7
B6
A6
AVDD1
AVSS1
BYP1
BYP2
CCDIN
BYP3
AVDD2
AVSS2
REFB
P
P
AO
AO
AI
AO
P
P
AO
A5
B5
A4
B4
A3
B3
B2
A2
REFT
SL
SDI
SCK
MSHUT
STROBE
DVSS
DVDD
AO
DI
DI
DI
DO
DO
P
P
NOTES
1
See Figure 50 for circuit configuration.
2
AI = Analog Input, AO = Analog Output, DI = Digital Input,
DO = Digital Output, DIO = Digital Input/Output, P = Power.
3
In Register Readback Mode
4
In Frame Transfer CCD Mode
Pin
Mnemonic Type
2
Description
A1
VD
DO
Vertical Sync Pulse
(Input for Slave Mode,
Output for Master Mode)
Horizontal Sync Pulse
(Input for Slave Mode,
Output for Master Mode)
External System Sync Input
Line or Field Designator
Output
Data Clock Output
CLPOB or PBLK Output
B1
HD
DO
C1
C2
SYNC
LD/FD
DI
DO
D1
D2
DCLK
CLPOB/
PBLK
NC
NC
DO/SDO
DO
DO
E1
E2
F2
Not Internally Connected
Not Internally Connected
Data Output (LSB)
(also Serial Data Output
3
)
Data Output
Data Output
Data Output
Data Output
Data Output
Data Output
Data Output
Data Output
Data Output (MSB)
Data Output Driver Supply
Data Output Driver Ground
CCD Substrate Bias
CCD Substrate Clock
(E-Shutter)
CCD Vertical Transfer Clock 1
CCD Vertical Transfer Clock 2
CCD Vertical Transfer Clock 3
CCD Vertical Transfer Clock 4
CCD Sensor Gate Pulse 1
(also V5
4
)
CCD Sensor Gate Pulse 2
(also V6
4
)
CCD Sensor Gate Pulse 3
(also V7
4
)
CCD Sensor Gate Pulse 4
(also V8
4
)
DO
F1
G2
G1
H2
H1
J2
J1
K2
K1
K3
K4
J3
J4
D1
D2
D3
D4
D5
D6
D7
D8
D9
DRVDD
DRVSS
VSUB
SUBCK
DO
DO
DO
DO
DO
DO
DO
DO
DO
P
P
DO
DO
K5
J5
K6
J6
K7
V1
V2
V3
V4
VSG1/V5
DO
DO
DO
DO
DO
J7
VSG2/V6
DO
K8
VSG3/V7
DO
J8
VSG4/V8
DO
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