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| 型號： | AD9895KBC |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | CCD Signal Processors with Precision Timing⑩ Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA64 |
| 封裝： | PLASTIC, CSPBGA-64 |
| 文件頁數(shù)： | 18/59頁 |
| 文件大小： | 599K |
| 代理商： | AD9895KBC |
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REV. A
–18–
AD9891/AD9895
Individual Vertical Sequences
To generate the individual vertical sequences or patterns shown
in Figure 18, five registers are required for each sequence.
Table VII summarizes these registers and their respective bit
lengths.
The start polarity (VTPPOL) determines the starting
polarity of
the vertical sequence and can be programmed high
or low. The first toggle position (VTPTOG1) and second
toggle position (VTPTOG2) are the pixel locations within the
line
where the pulse transitions. A third toggle position
(VTPTOG3) is also available for sequences 0 through 7. All
toggle positions are 10-bit values, which limits the placement of
a pulse to within 1024 pixels of a line. A separate register,
VSTART, sets the start position of the sequence within the line
(see Individual Vertical Regions section). The Length
(VTPLEN) Register determines the number of pixels between
each of the pulse repetitions, if any repetitions have been
programmed. The number of repetitions (VTPREP) simply
determines the number of pulse repetitions desired within a
single line. Programming
“
1
”
for VTPREP gives a single
pulse, while setting to
“
0
”
will provide a fixed dc output based
on the start polarity value. There is a total of 12 individual
sequences that may be programmed.
When specifying the individual regions, each sequence may be
assigned to any of the V1
–
V4 outputs. For example, Figure 19
shows a typical 4-phase V-clock arrangement. Two different
sequences are needed to generate the different pulsewidths.
The use of individual start positions for V1
–
V4 allows the four
outputs to be generated from two sequences. Figure 20 shows a
slightly different V-clock arrangement in which V2, V3, and V4
are simply shifted and/or inverted versions of V1. Only one
individual sequence is needed because all signals have the same
pulsewidth. The invert sequence registers (VINV) are used for
V3 and V4 (see Table VII).
Note that for added flexibility, the VTPPOL Registers (Start
Polarity) may be used as an extra toggle position.
Table VII. Individual VTP Sequence Parameters
Register
Length
Range
Description
VTPPOL
VTPTOG1
VTPTOG2
VTPTOG3
VTPLEN
VTPREP
1b
10b
10b
10b
10b
12b
High/Low
0
–
1023 Pixel Location
0
–
1023 Pixel Location
0
–
1023 Pixel Location
0
–
1023 Pixels
0
–
4095 Pulses
Starting Polarity of Vertical Transfer Pulse for Each Sequence 0
–
11
First Toggle Position within Line for Each Sequence 0
–
11
Second Toggle Position within Line for Each Sequence 0
–
11
Third Toggle Position within Line for Each Sequence 0
–
7
Length between Pulse Repetitions for Each Sequence 0
–
11
Number of Pulse Repetitions for Each Sequence 0
–
11 (0 = DC Output)
HD
V1–V4
PROGRAMMABLE SETTINGS FOR EACH SEQUENCE:
1: START POLARITY
2: 1ST TOGGLE POSITION
3: 2ND TOGGLE POSITION (THERE IS ALSO A 3RD TOGGLE POSITION AVAILABLE FOR SEQUENCES 0 TO 7)
4: LENGTH BETWEEN REPEATS
5: NUMBER OF REPEATS
START POSITION OF SEQUENCE IS INDIVIDUALLY PROGRAMMABLE FOR EACH V1–V4 OUTPUT
4
5
1
2
3
Figure 18. Individual Vertical Sequence Programmability
V1
V2
V1 USES SEQUENCE 0
V3
V4
HD
V2 USES SEQUENCE 0,
WITH DIFFERENT START POSITION
V3 USES SEQUENCE 1
V4 USES SEQUENCE 1,
WITH DIFFERENT START POSITION
Figure 19. Example of Separate V1–V4 Signals Using Two Individual Sequences
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