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參數(shù)資料
| 型號(hào)： | AD9895KBC |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | CCD Signal Processors with Precision Timing⑩ Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA64 |
| 封裝： | PLASTIC, CSPBGA-64 |
| 文件頁(yè)數(shù)： | 25/59頁(yè) |
| 文件大?。?/td> | 599K |
| 代理商： | AD9895KBC |
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REV. A
AD9891/AD9895
–25–
V1
V2
V1 USES SEQUENCE 0
V3
V4
HD
V2 USES SEQUENCE 0
V3 USES SEQUENCE 1
V4 USES SEQUENCE 1
V5
V6
V5 USES SEQUENCE 0
V7
V8
V6 USES SEQUENCE 0
V7 USES SEQUENCE 1
V8 USES SEQUENCE 1
ACTIVE
IMAGE
AREA
STORAGE
AREA
Figure 28. Example of Frame Transfer CCD Mode using V1–V8
The frame transfer CCD also requires additional timing con
trol
when decimating the image for Preview Mode. The
AD9891/AD9895 contain registers to independently stop the
operation of the V5
–
V8 outputs while the V1
–
V4 outputs con-
tinue to run or to stop the V1
–
V4 outputs, while the V5
–
V8
outputs remain operational. The FREEZE and RESUME Regis-
ters specify the pixel locations within each line of a region where
the V1
–
V4 or V5
–
V8 clock outputs will start to hold their state,
and
where they will resume normal operation. FREEZE and
RESUME can be used in any region during the frame readout.
Vertical Sensor Gate (Shift Gate) Timing
With an interline CCD, the vertical sensor gates (VSG) are used to
transfer the pixel charges from the light-sensitive image area into the
light-shielded vertical registers. When a mechanical shutter is not being
used, this transfer will effectively end the exposure period during the
image acquisition. From the light-shield vertical registers, the image
is then read out line-by-line by using the vertical transfer pulses
V1
–
V4 in conjunction with the high speed horizontal clocks.
VD
HD
PROGRAMMABLE SETTINGS FOR EACH SEQUENCE:
1: START POLARITY OF PULSE
2: 1ST TOGGLE POSITION
3: 2ND TOGGLE POSITION
4: ACTIVE LINE FOR VSG PULSE WITHIN THE FIELD
VSG1–VSG8
4
1
2
3
Figure 29. Vertical Sensor Gate Pulse Placement
Table XIII. Sensor Gate Register Parameters
Register
SGPOL
SGTOG1
SGTOG2
SGACTLINE
SGSEL
SGMASK
Length
1b
12b
12b
12b
2b
8b
Range
High/Low
0
–
4095 Pixel Location
0
–
4095 Pixel Location
0
–
4095 Pixel Location
Sequence 0
–
3
8 Individual Bits
Description
Sensor Gate Starting Polarity for Sequence 0
–
3
First Toggle Position for Sequence 0
–
11
Second Toggle Position for Sequence 0
–
11
Line in Field where VSG1
–
VSG8 Are Active
Selects Sequence 0
–
3 for VSG1
–
VSG8
Masking for any of VSG1
–
VSG8 Signals (0 = On, 1 = Mask)
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