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| 型號(hào)： | AD9895KBC |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費(fèi)家電 |
| 英文描述： | CCD Signal Processors with Precision Timing⑩ Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA64 |
| 封裝： | PLASTIC, CSPBGA-64 |
| 文件頁(yè)數(shù)： | 43/59頁(yè) |
| 文件大小： | 599K |
| 代理商： | AD9895KBC |
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REV. A
AD9891/AD9895
–43–
Table XIX. AFE Register Map
Bit
Width
Default
Value
Address
Content
Register Name
Register Description
00
01
02
03
04
05
06
07
08
09
0A
[5:0]
[1:0]
[5:0]
[3:0]
[5:0]
[1:0]
[5:0]
[5:0]
[5:0]
[5:0]
[5:0]
6
2
6
4
6
2
6
6
6
6
6
10
00
05
01
00
02
00
00
00
00
00
OPRMODE[5:0]
OPRMODE[7:6]
CCDGAIN[5:0]
CCDGAIN[9:6]
REFBLACK[5:0]
REFBLACK[7:6]
CTLMODE
PXGA GAIN0
PXGA GAIN1
PXGA GAIN2
PXGA GAIN3
AFE Operation Mode (See Table XXXI.)
VGA Gain (Defaults to 2 dB)
Black Clamp Level
Control Mode (See Table XXXI.)
PxGA
Color 0 Gain
PxGA
Color 1 Gain
PxGA
Color 2 Gain
PxGA
Color 3 Gain
Table XX. MISCELLANEOUS/EXTRA Register Map
Bit
Width
Default
Value
Address
Content
Register Name
Register Description
010
017
018
019
[5:0]
[0]
[0]
[5:0]
6
1
1
6
00
00
00
00
INTIAL2
SW_RESET
OUT_CONT
UPDATE[5:0]
See Power-Up Sequence. Should be set to
“
4.
”
Software Reset (1 = Reset All Registers to Default)
Output Control (0 = Make All Outputs DC Inactive)
Serial Data Update Control. Sets the line (HD)
within the field for the serial data update to occur.
01A
01B
01C
01D
01E
[5:0]
[0]
[0]
[5:0]
[0]
6
1
1
6
1
00
00
00
00
00
UPDATE[11:6]
PREVENTUPDATE
READBACK
DOUTPHASE
DCLKMODE
Prevents the Update of the VD Updated Registers
Serial Interface Readback Enable
DOUT Phase Control
DCLK Mode (0 = DCLK Tracks DOUT Phase,
1 = DCLK Is CLO, i.e., CLI Inverse)
Divide CLI Input Clock by 2
Disable CCDIN DC Restore Circuit during PBLK
(1 = Disable)
Reset Internal Field Pulse Value (0 = Next Field
Odd, 1 = Next Field Even)
Re-time H1/H2 HBLK to Internal H1 Clock
Re-time H3/H4 HBLK to Internal H3 Clock
External Synchronization Enable (1 = Enable)
SYNC Active Polarity (0 = Active LOW)
Suspend Clocks during SYNC Active (1 = Suspend)
Assign LD/FD Output (0 = FD, 1 = LD)
Assign CLPOB/PBLK Output (0 = CLPOB,
1 = PBLK)
TG Core Reset_bar (0 = Hold TG Core in Reset,
1 = Resume Operation)
Frame Transfer CCD Mode (1 = VSG1
–
VSG4
Become V5
–
V8 Out)
See Power-Up Sequence. Should be set to
“
53.
”
CLPDM = CLPOB when Set to 1 (Only CLPOB
Registers Used).
Delay from DCLK to DOUT (0 = No Delay,
1 = 4 ns, 2 = 8 ns, 3 = 12 ns)
CLO Oscillator Power-Down (0 = Oscillator Is
Powered Down)
01F
020
[0]
[0]
1
1
00
00
CLIDIVIDE
DISABLERESTORE
021
[0]
1
01
FIELDVAL
022
023
024
025
026
027
028
[0]
[0]
[0]
[0]
[0]
[0]
[0]
1
1
1
1
1
1
1
00
00
00
00
00
00
00
H1HBLKRETIME
H3HBLKRETIME
SYNCENABLE
SYNCPOL
SYNCSUSPEND
OUTPUTLD
OUTPUTPBLK
029
[0]
1
00
TGCORE_RSTB
02A
[0]
1
00
FTRANCCD
02B
031
[5:0]
[0]
6
1
00
01
INTIAL1
SINGLE_CLAMP
032
[1:0]
2
02
DOUT_DELAY
033
[0]
1
01
OSC_PWRDOWN
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