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參數(shù)資料
| 型號： | AD9895KBC |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | CCD Signal Processors with Precision Timing⑩ Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA64 |
| 封裝： | PLASTIC, CSPBGA-64 |
| 文件頁數(shù)： | 39/59頁 |
| 文件大?。?/td> | 599K |
| 代理商： | AD9895KBC |
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REV. A
AD9891/AD9895
–39–
VERTICAL TIMING EXAMPLE
Figure 49 shows an example CCD timing chart for an interlaced
readout. Each field can be broken down into four separate region
areas. The vertical region change positions (RCPs) will set the
line boundaries for each region area, and the region pointers will
assign a unique region to each region area.
Region Area 0 is a high speed vertical shift region. Sweep Mode
can be used to generate this timing operation, with the desired
number of high speed vertical pulses needed to
“
clean
”
the
charge from the CCD
’
s vertical registers.
Region Area 1 consists of only two lines and uses standard
single line vertical shift timing. The timing of this region area
will be the same as the timing in Region Area 3.
Region Area 2 is the sensor gate line, where the VSG pulses trans-
fer the image into the vertical CCD registers. This region will
require the use of the second vertical sequence for SG lines.
Region Area 3 also uses the standard single line vertical shift
timing, the same timing as Region Area 1.
In summary, three unique regions are required to support the four
region areas, since Region Areas 1 and 3 use the same timing.
Some of the timing parameters will need to be adjusted to read out
the second field, such as the sensor gate pulse and line location.
VD
HD
V1/VSG1
V2
V3/VSG2
V4
SUBCK
MSHUT
VSUB
CCD
OUT
EXPOSURE PERIOD (
t
EXP
)
INTERLACED READOUT PERIOD
REGION
AREA 1
REGION
AREA 2
REGION
AREA 0
REGION
AREA 3
1
3
5
7
9
1
n
n
OPEN
CLOSE
2
4
6
8
1
1
n
n
OPEN
1
1
1
1
1
1
1
2
Figure 49. Vertical Timing Example—Separate Regions
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