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| 型號： | AD9895KBC |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 消費家電 |
| 英文描述： | CCD Signal Processors with Precision Timing⑩ Generator |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PBGA64 |
| 封裝： | PLASTIC, CSPBGA-64 |
| 文件頁數(shù)： | 22/59頁 |
| 文件大小： | 599K |
| 代理商： | AD9895KBC |
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REV. A
–22–
AD9891/AD9895
Second Vertical Sequence During VSG Lines
Most CCDs require additional vertical timing during the sensor
gate line. The AD9891/AD9895 supports the option to output a
second set of sequences for V1
–
V4 during the line when the sen-
sor gates VSG1
–
VSG4 are active. Figure 25 shows a typical VSG
line, which includes two separate sets of vertical sequences on V1
–
V4. The sequences at the start of the line are the same as those
generated in the previous line. But the second sequence only
occurs in the line where the VSG signals are active. To select the
sequences used for the second sequence, the registers in
Table XI are used. To enable the second set of sequences during
the VSG line, the VTP_SGLINEMODE is set HIGH. As with
the standard vertical regions, each V1
–
V4 output has an indi-
vidual start position, programmed in the VxSTART_SGLINE
Registers. Each V1
–
V4 output can select from the pool of 12
unique sequences using individual sequence pointer registers,
VxSPTR_SGLINE. Also, any sequence may be inverted for a
particular V1
–
V4 output by using the VxINV_SGLINE Registers.
Vertical Sweep Mode Operation
The AD9891/AD9895 contains a special mode of vertical timing
operation called Sweep Mode. This mode is used to generate a
large number of repetitive pulses that span across multiple HD
lines. One example of where this mode may be needed is at the
start of the CCD readout operation. At the end of the image
exposure, but before the image is transferred by the sensor gate
pulses, the vertical interline CCD Registers should be
“
clean
”
of
all charge. This can be accomplished by quickly shifting out any
charge with a long series of pulses on the V1
–
V4 outputs. De-
pending on the vertical resolution of the CCD, up to two or
three thousand clock cycles will be needed to shift the charge out
of each vertical CCD line. This operation will span across mul-
tiple HD line lengths. Normally, the AD9891/AD9895 sequences
are contained within one HD
line length. But when Sweep Mode
is enabled, the HD boundaries
will be ignored until the region is
finished. To enable Sweep Mode
within any region, program
the appropriate SWEEP (0
–
4) Registers to HIGH.
Figure 26 shows an example of the Sweep Mode operation. The
number of vertical pulses needed will depend on the vertical
resolution of the CCD. The V1
–
V4 output signals are generated
using the Individual Vertical Sequence Registers (shown in Table
VII). A single pulse is created using the first, second, and third
toggle positions, and then the number of repeats is set to the
number of vertical shifts required by the CCD. The maximum
number of repeats is 4096 in this mode, using the VTPREP
Register. This produces a pulse train of the appropriate length.
Normally, the pulse train would be truncated at the end of the
HD line length. But with Sweep Mode enabled for this region, the
HD boundaries will be ignored. In Figure 26, the sweep region
occupies 23 HD
lines. After the Sweep Mode region is completed,
normal sequence operation will resume
in the next region
.
Table XI. Second Vertical Sequence Registers During SG Lines
Register Name
Length
Range
Description
VTP_SGLINEMODE
VxSTART_SGLINE
VxSPTR_SGLINE
VxINV_SGLINE
1b
12b
4b
1b
HIGH/LOW
0
–
4095 Pixel Location
0
–
11 Sequence #
HIGH/LOW
To Turn on Second Sequences during SG Line, Set = HIGH
Sequence Start Position for Each Vx Output for SG Line Sequence
Sequence Pointer for Vx Output during second SG Line Sequence
When HIGH, the Polarity of Sequence VxSPTRFIRST Is Inverted
x is the V-output from 1
–
4.
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