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參數(shù)資料
| 型號： | AD9891 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CCD Signal Processors with Precision Timing⑩ Generator |
| 中文描述： | CCD信號處理器，精確定時⑩發(fā)生器 |
| 文件頁數(shù)： | 42/59頁 |
| 文件大?。?/td> | 599K |
| 代理商： | AD9891 |
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REV. A
–42–
AD9891/AD9895
Table XVIII. SG-Line Updated Registers
Register
Description
SUBCKPOL
SUBCK1TOG1
SUBCK1TOG2
SUBCK2TOG1
SUBCK2TOG2
SUBCKNUM
SUBCKSUPPRESS
SUBCK Start Polarity
SUBCK First Toggle Position
SUBCK Second Toggle Position
Second SUBCK First Toggle Position
Second SUBCK Second Toggle Position
Total Number of SUBCKs per Field
Number of SUBCKs to Suppress after
VSG Line
NOTES ON REGISTER LISTING
1. Registers larger than six bits occupy two adjacent addresses.
When writing to these registers, the lower address contain-
ing the least significant data bits should be written to first.
The data for both addresses should be written to avoid
corruption of register data.
2. All addresses and default values are expressed in hexadecimal.
3. All registers are VD/HD updated as shown in Figure 52, except
for the registers indicated in Table XVII, which are SL updated.
4. The registers indicated in Table XVIII are not updated by
SL or VD/HD, but are updated at the HD line following
the VSG line.
Table XVII. SL-Updated Register
Register
Description
OPRMODE
CTLMODE
SW_RESET
READBACK
AFE Operation Modes
AFE Control Modes
Software Reset Bit
Enables Serial Register Readback
Mode
Resets Internal Field Pulse.
Retimes the H1 HBLK to Internal
Clock
Retimes the H3 HBLK to Internal
Clock
External Synchronization Enable
External SYNC Active Polarity
SYNC Suspend while Active
Reset Bar Signal for Internal TG
Core
Frame Transfer CCD Mode
H1/H2 Polarity Control
H1 Positive Edge Location
H1 Negative Edge Location
H3/H4 Polarity Control
H3 Positive Edge Location
H3 Negative Edge Location
H1 Drive Current
H2 Drive Current
H3 Drive Current
H4 Drive Current
RG Polarity
RG Positive Edge Location
RG Negative Edge Location
SHP Sample Location
SHD Sample Location
VD/HD Master/Slave Timing Mode
VD/HD Active Polarity
Sets CLPDM = CLPOB
Sets the Output Delay of DOUT
Powers Down the CLO Oscillator
VD/HD Active Polarity
FIELDVAL
H1HBLKRETIME
H3HBLKRETIME
SYNCENABLE
SYNCPOL
SYNCSUSPEND
TG_CORE RSTB
FFTRANCCD
H12POL
H1POSLOC
H1NEGLOC
H34POL
H3POSLOC
H3NEGLOC
H1DRV
H2DRV
H3DRV
H4DRV
RGPOL
RGPOSLOC
RGNEGLOC
SHPLOC
SHDLOC
MASTER
VDHDPOL
SINGLE_CLAMP
DOUT_DELAY
OSC_PWRDOWN
VDHDPOL
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