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參數(shù)資料
| 型號(hào)： | AD9891 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CCD Signal Processors with Precision Timing⑩ Generator |
| 中文描述： | CCD信號(hào)處理器，精確定時(shí)⑩發(fā)生器 |
| 文件頁數(shù)： | 15/59頁 |
| 文件大小： | 599K |
| 代理商： | AD9891 |
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REV. A
AD9891/AD9895
–15–
HORIZONTAL CLAMPING AND BLANKING
The AD9891/AD9895
’
s horizontal clamping and blanking pulses
are fully programmable to suit a variety of applications. As with
the vertical timing generation, individual sequences are defined
for each signal, which are then organized into multiple regions
during image readout. This allows the dark pixel clamping and
blanking patterns to be changed at each stage of the readout in
order to accommodate different image transfer timing and high
speed line shifts.
Individual CLPOB, CLPDM, and PBLK Sequences
The AFE horizontal timing consists of CLPOB, CLPDM, and
PBLK, as shown in Figure 13. These three signals are indepen-
dently programmed using the registers in Table III. SPOL is
the start polarity for the signal, and TOG1 and TOG2 are the
first and second toggle positions of the pulse. All three signals
are active low and should be programmed accordingly. Up to
four individual sequences can be created for each signal.
To simplify the programming requirements, the CLPDM signal
will track the CLPOB signal by default. If separate control of
the CLPDM signal is desired, the SINGLE_CLAMP Register
(Addr x031) should be set LOW.
Individual HBLK Sequences
The HBLK programmable timing shown in Figure 14 is similar
to CLPOB, CLPDM, and PBLK. However, there is no start
polarity control. Only the toggle positions are used to designate
the start and the stop positions of the blanking period. Addition-
ally, there is a polarity control, HBLKMASK, that designates the
polarity of the horizontal clock signals H1
–
H4 during the blank-
ing period. Setting HBLKMASK high will set H1 = H3 = Low
and H2 = H4 = High during the blanking, as shown in Figure 15.
Up to four individual sequences are available for HBLK.
Horizontal Sequence Control
The AD9891/AD9895 use sequence change positions (SCP)
and
sequence pointers (SPTR) to organize the individual hori-
HD
CLPOB
CLPDM
PBLK
PROGRAMMABLE SETTINGS:
1: START POLARITY (CLAMP AND BLANK REGION ARE ACTIVE LOW)
2: 1ST TOGGLE POSITION
3: 2ND TOGGLE POSITION
CLAMP
CLAMP
1
2
3
Figure 13. Clamp and Preblank Pulse Placement
HD
HBLK
PROGRAMMABLE SETTINGS:
1: 1ST TOGGLE POSITION = START OF BLANKING
2: 2ND TOGGLE POSITION = END OF BLANKING
BLANK
BLANK
1
2
Figure 14. Horizontal Blanking (HBLK) Pulse Placement
HD
HBLK
THE POLARITY OF H1 DURING BLANKING IS PROGRAMMABLE (H2 IS OPPOSITE POLARITY OF H1)
H1/H3
H1/H3
H2/H4
Figure 15. HBLK Masking Control
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| AD9891KBC | 制造商:Rochester Electronics LLC 功能描述:10 BIT 20 MSPS, 5V/3V AFETG - Bulk 制造商:Analog Devices 功能描述: |
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| AD9895KBCRL | 制造商:Analog Devices 功能描述:AFE Video 1ADC 12-Bit 3V/5V 64-Pin CSP-BGA T/R |
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