參數(shù)資料
型號(hào)： AD9891
廠商： Analog Devices, Inc.
英文描述： CCD Signal Processors with Precision Timing⑩ Generator
中文描述： CCD信號(hào)處理器，精確定時(shí)⑩發(fā)生器
文件頁(yè)數(shù)： 37/59頁(yè)
文件大小： 599K
代理商： AD9891
REV. A
AD9891/AD9895
–37–
V
H
USE SEQUENCE 2
USE SEQUENCE 3
SEQUENCE 2 (OPTIONAL)
HORIZONTAL CCD REGISTER
EFFECTIVE IMAGE AREA
28 DUMMY PIXELS
48 OB PIXELS
4 OB PIXELS
10 VERTICAL OB LINES
2 VERTICAL OB LINES
Figure 45. Example CCD Configuration
VERTICAL SHIFT
VERT SHIFT
SEQUENCE 1: VERTICAL BLANKING
CCDIN
SHP
SHD
H1/H3
H2/H4
HBLK
PBLK
CLPOB
CLPDM
DUMMY
INVALID PIXELS
INVALID PIX
CLPDM PULSE MAY BE USED DURING HORIZONTAL DUMMY PIXELS IF THE H-CLOCKS ARE USED DURING VERTICAL BLANKING.
Figure 46. Horizontal Sequences During Vertical Blanking
HORIZONTAL TIMING SEQUENCE EXAMPLE
Figure 45 shows an example CCD layout. The horizontal regis-
ter contains 28 dummy pixels that will occur on each line
clocked from the CCD. In the vertical direction, there are 10
optical
black (OB) lines at the front of the readout and two at
the back of the readout. The horizontal direction has four OB
pixels in the front and 48 in the back.
To configure the AD9891/AD9895 horizontal signals for this
CCD, three sequences can be used. Figure 46 shows the first
sequence to be used during vertical blanking. During this time,
there are no valid OB pixels from the sensor, so the CLPOB and
CLPDM signals are not used. In some cases, if the horizontal
clocks are used during this time, the CLPDM signal may be used
to keep the AD9891/AD9895
’
s input clamp partially settled.
PBLK may be enabled during this time because no valid data is
available.
Figure 47 shows the recommended sequence for the vertical OB
interval. The clamp signals are used across the whole lines in
order to stabilize the clamp loops of the AD9891/AD9895.
Figure 48 shows the recommended sequence for the effective
pixel readout. The 48 OB pixels at the end of each line are used
for the CLPOB and CLPDM signals.
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