- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄17065 > AD9788-DPG2-EBZ (Analog Devices Inc)BOARD EVALUATION FOR AD9788 PDF資料下載
參數(shù)資料
| 型號(hào)： | AD9788-DPG2-EBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 44/64頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVALUATION FOR AD9788 |
| 設(shè)計(jì)資源： | Powering the AD9788 Using ADP2105 for Increased Efficiency (CN0141) |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | * |
| DAC 的數(shù)量： | 2 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 800M |
| 數(shù)據(jù)接口： | 串行 |
| 設(shè)置時(shí)間： | 22ms |
| DAC 型： | 電流 |
| 工作溫度： | -40°C ~ 85°C |
| 已供物品： | * |
| 已用 IC / 零件： | AD9788 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁當(dāng)前第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁
AD9785/AD9787/AD9788
Rev. A | Page 49 of 64
Configuring the PLL Band Select Value
The PLL VCO has a valid operating range from approximately
1.0 GHz to 2.0 GHz covered in 63 overlapping frequency bands
as shown in Table 35. For any desired VCO output frequency,
there are multiple valid PLL band select values. Note that the
data shown in Table 35 is for a typical device. Device-to-device
variations can shift the actual VCO output frequency range by
30 MHz to 40 MHz. Also, the VCO output frequency varies as
a function of temperature. Therefore, it is required that the
optimal PLL band select value be determined for each
individual device at the particular operating temperature.
The device has an automatic PLL band select feature on chip.
When enabled, the device determines the optimal PLL band
setting for the device at the given temperature. This setting holds
for a ±60°C temperature swing in ambient temperature. If the
device operates in an environment that experiences a larger
temperature swing, an offset should be applied to the automat-
ically selected PLL band. The following procedure outlines a
method for setting the PLL band select value for a device
operating at a particular temperature that holds for a change in
ambient temperature over the total 40°C to +85°C operating
range of the device without further user intervention. (Note that
REFCLK must be applied to the device during this procedure.)
Configuring PLL Band Select with Temperature Sensing
The values of N1 (Register 0x04, Bits [14:13]) and N2
(Register 0x04, Bits [12:11]) should be programmed along
with the PLL settings shown in Table 34.
1.
Set the PLL Band Select [5:0] value (Register 0x04,
Bits [7:2]) to 63 to enable PLL auto mode.
2.
Wait for the PLL_LOCK pin or the PLL lock indicator
(Register 0x09, Bit 3) to go high. This should occur
within 5 ms.
3.
Read back the 6-bit PLL band select value (Register 0x04,
Bits [7:2]).
4.
Based on the temperature when the PLL auto mode is
enabled, set the PLL band indicated in Table 36 or Table 37
by rewriting the readback values into the PLL Band Select
[5:0] parameter (Register 0x04, Bits [7:2]).
Table 36. Setting Optimal PLL Band for Lower Range
(0 to 31) Bands
System Start-Up Temperature
Set PLL Band to
40°C to 10°C
Readback Band + 2
10°C to +15°C
Readback Band + 1
15°C to 55°C
Readback Band
55°C to 85°C
Readback Band 1
Table 37. Setting Optimal PLL Band for Higher Range
(32 to 62) Bands
System Start-Up Temperature
Set PLL Band to
40°C to 30°C
Readback Band + 3
30°C to 10°C
Readback Band + 2
10°C to +15°C
Readback Band + 1
15°C to 55°C
Readback Band
55°C to 85°C
Readback Band 1
Known Temperature Calibration with Memory
The procedure in the Configuring PLL Band Select with
Temperature Sensing section requires temperature sensing
upon start-up or reset of the device to choose the optimal PLL
band select value to hold over the entire operating temperature
range. If temperature sensing is not available in the system,
another option is to use the automatic PLL band select to
determine the optimal setting for the device when the device is
in a factory environment where the temperature is known. The
optimal band can then be stored in nonvolatile memory.
Whenever the system is powered up or restarted, the optimal
value can be loaded back into the device.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SLPX223M025E7P3 | CAP ALUM 22000UF 25V 20% SNAP |
| EMA10DTKS | CONN EDGECARD 20POS DIP .125 SLD |
| EVAL-AD5392EBZ | BOARD EVAL FOR AD5392 |
| 380LX682M025H022 | CAP ALUM 6800UF 25V 20% SNAP |
| DC941A | BOARD DELTA SIGMA ADC LTC2482 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9788-EBZ | 制造商:Analog Devices 功能描述:Evaluation Board For AD9788 制造商:Analog Devices 功能描述:DUAL 16B, D-A CONVERTER - Bulk 制造商:Analog Devices 功能描述:Digital to Analog Eval. Board |
| AD9788MOD-EBZ | 制造商:Analog Devices 功能描述:DUAL 12-/14-/16-BIT 800 MSPS DAC WITH LOW POWER 32-BIT COMPLEX NCO 制造商:Analog Devices 功能描述:DUAL 16B, D-A CONVERTER - Bulk |
| AD9789BBC | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 14 Bit 2.5 GSPS D-A Converter RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
| AD9789BBCRL | 制造商:Analog Devices 功能描述:QAM Encoder/Interpolator/Upconverter 164-Pin CSP-BGA T/R 制造商:Analog Devices 功能描述:QAM ENCODER/INTERPOLATOR/UPCNVRTR 164CSPBGA - Tape and Reel 制造商:Analog Devices 功能描述:IC DAC 14BIT 2.4GSPS 4CH 164BGA 制造商:Analog Devices Inc. 功能描述:Digital to Analog Converters - DAC 14 Bit 2.5 GSPS D-A Converter 制造商:Analog Devices Inc. 功能描述:Digital to Analog Converters - DAC 14B 2400MSPS RF w/ 4CH Signal Process 制造商:Analog Devices 功能描述:CONVERTER - DAC |
| AD9789BBCZ | 功能描述:數(shù)模轉(zhuǎn)換器- DAC 14 Bit 2.5 GSPS D-A Converter RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。