參數(shù)資料
型號： AD9788-DPG2-EBZ
廠商： Analog Devices Inc
文件頁數(shù)： 24/64頁
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD9788
設(shè)計(jì)資源： Powering the AD9788 Using ADP2105 for Increased Efficiency (CN0141)
標(biāo)準(zhǔn)包裝： 1
系列： *
DAC 的數(shù)量： 2
位數(shù)： 16
采樣率（每秒）： 800M
數(shù)據(jù)接口： 串行
設(shè)置時間： 22ms
DAC 型： 電流
工作溫度： -40°C ~ 85°C
已供物品： *
已用 IC / 零件： AD9788
AD9785/AD9787/AD9788
Rev. A | Page 30 of 64
The Auxiliary DAC 1 control register comprises two bytes located at Address 0x06. These bits are routed directly to the periphery of the
digital logic. No digital functionality within the main digital block is required.
Table 16. Auxiliary DAC 1 Control Register
Address
Bit
Name
Description
0x06
[15]
Auxiliary DAC 1 sign
0: Default. If the Auxiliary DAC 1 sign bit is cleared, the Aux DAC 1 sign is positive.
Pin 90 is the active pin.
1: If the Auxiliary DAC 1 sign bit is set, the Aux DAC 1 sign is negative. Pin 89 is the
active pin.
[14]
Auxiliary DAC 1
current direction
0: Default. If the Auxiliary DAC 1 current direction bit is cleared, the Aux DAC 1 sources
current.
1: If the Auxiliary DAC 1 current direction bit is set, the Aux DAC 1 sinks current.
[13]
Auxiliary DAC 1
power-down
0: Default. If the Auxiliary DAC 1 power-down bit is cleared, the Aux DAC 1 is active.
1: If the Auxiliary DAC 1 power-down bit is set, the Aux DAC 1 is inactive and enters a
low power state.
[12:10]
Reserved
Reserved for future use.
[9:0]
Auxiliary DAC 1 data
These bits are the Auxiliary DAC 1 gain adjustment bits.
The Q DAC control register comprises two bytes located at Address 0x07. These bits are routed directly to the periphery of the digital
logic. No digital functionality within the main digital block is required.
Table 17. Q DAC Control Register
Address
Bit
Name
Description
0x07
[15]
Q DAC sleep
0: Default. If the Q DAC sleep bit is cleared, the Q DAC is active.
1: If the Q DAC sleep bit is set, the Q DAC is inactive and enters a low power state.
[14]
Q DAC power-down
0: Default. If the Q DAC power-down bit is cleared, the Q DAC is active.
1: If the Q DAC power-down bit is set, the Q DAC is inactive and enters a low power state.
[13:10]
Reserved
Reserved for future use.
[9:0]
Q DAC gain adjustment
These bits are the Q DAC gain adjustment bits.
The Auxiliary DAC 2 control register comprises two bytes located at Address 0x08. These bits are routed directly to the periphery of the
digital logic. No digital functionality within the main digital block is required.
Table 18. Auxiliary DAC 2 Control Register
Address
Bit
Name
Description
0x08
[15]
Auxiliary DAC 2 sign
0: Default. If the Auxiliary DAC 2 sign bit is cleared, the Aux DAC 2 sign is positive.
Pin 86 is the active pin.
1: If the Auxiliary DAC 2 sign bit is set, the Aux DAC 2 sign is negative. Pin 87 is the
active pin.
[14]
Auxiliary DAC 2
current direction
0: Default. If the Auxiliary DAC 2 current direction bit is cleared, the Aux DAC 2 sources
current.
1: If the Auxiliary DAC 2 current direction bit is set, the Aux DAC 2 sinks current.
[13]
Auxiliary DAC 2
power-down
0: Default. If the Auxiliary DAC 2 power-down bit is cleared, the Aux DAC 2 is active.
1: If the Auxiliary DAC 2 power-down bit is set, the Aux DAC 2 is inactive and enters
a low power state.
[12:10]
Reserved
Reserved for future use.
[9:0]
Auxiliary DAC 2 data
These bits are the Auxiliary DAC 2 gain adjustment bits.
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