參數(shù)資料
型號(hào)： AD9788-DPG2-EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 29/64頁(yè)
文件大?。?/td> 0K
描述： BOARD EVALUATION FOR AD9788
設(shè)計(jì)資源： Powering the AD9788 Using ADP2105 for Increased Efficiency (CN0141)
標(biāo)準(zhǔn)包裝： 1
系列： *
DAC 的數(shù)量： 2
位數(shù)： 16
采樣率（每秒）： 800M
數(shù)據(jù)接口： 串行
設(shè)置時(shí)間： 22ms
DAC 型： 電流
工作溫度： -40°C ~ 85°C
已供物品： *
已用 IC / 零件： AD9788
AD9785/AD9787/AD9788
Rev. A | Page 35 of 64
Setting the Frequency of DATACLK
The DATACLK signal is derived from the internal DAC sample
clock, DACCLK. The frequency of DATACLK output depends
on several programmable settings. The relationship between the
frequency of DACCLK and DATACLK is
P
IF
f
DACCLK
DATACLK
where the variables have the values shown in Table 26.
Table 26. DACCLK to DATACLK Divisor Values
Variable
Value
Address
Register
Bits
IF
Interpolation factor
0x01
[7:6]
P
0.5 (if single port is enabled)
1 (if dual port is selected)
0x01
[4]
INPUT DATA REFERENCED TO REFCLK
In some systems, it may be more convenient to use the REFCLK
input instead of the DATACLK output as the input data timing
reference. If the frequency of DACCLK is equal to the frequency
of the data input (PLL is bypassed and no interpolation is used),
the timing parameter “Data with respect to REFCLK” shown in
Table 25 applies directly without further considerations. If the
frequency of DACCLK is greater than the frequency of the data
input, a divider is used to generate the internal data sampling clock
(DCLK_SMP). This divider creates a phase ambiguity between
REFCLK and DCLK_SMP, which, in turn, causes a sampling
time uncertainty. To establish fixed setup and hold times for the
data interface, this phase ambiguity must be eliminated.
To eliminate the phase ambiguity, the SYNC_I input pins
(Pin 13 and Pin 14) must be used to synchronize the data to
a specific DCLK_SMP phase. The specific steps for accom-
plishing this are detailed in the Device Synchronization section.
The timing relationships between SYNC_I, DACCLK, REFCLK,
and the input data are shown in Figure 49 through Figure 51.
DACCLK
REFCLK
SYNC_I
tS_SYNC
tH_SYNC
INPUT
DATA
tSREFCLK
tHREFCLK
07
098
-1
1
3
Figure 49. REFCLK 2×
DACCLK
REFCLK
INPUT
DATA
tSREFCLK
tHREFCLK
tS_SYNC
tH_SYNC
SYNC_I
07
09
8-
1
4
Figure 50. REFCLK 4×
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