參數(shù)資料
型號： AD9260EB
廠商： Analog Devices, Inc.
英文描述： High-Speed Oversampling CMOS ADC with 16-Bit Resolution at a 2.5 MHz Output Word Rate
中文描述： 高速16位分辨率在2.5 MHz的輸出字速率采樣的CMOS模數(shù)轉(zhuǎn)換器
文件頁數(shù)： 9/36頁
文件大?。?/td> 572K
代理商： AD9260EB
–9–
REV. B
AD9260
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9260 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high-energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
Temperature
Range
–
40
°
C to +85
°
C
Package
Description
Package
Option
*
Model
AD9260AS
AD9260EB
44-Lead MQFP
Evaluation Board
S-44
*
S = Metric Quad Flatpack.
THERMAL CHARACTERISTICS
Thermal Resistance
44-Lead MQFP
θ
JA
= 53.2
°
C/W
θ
JC
= 19
°
C/W
ABSOLUTE MAXIMUM RATINGS
*
With
Respect
to
AVSS
DVSS
DVSS
DVDD
DRVSS
AVSS
AVSS
Parameter
AVDD
DVDD
AVSS
AVDD
DRVDD
DRVSS
REFCOM
CLK, MODE, READ,
CS
,
RESET
Digital Outputs
VINA, VINB,
CML, BIAS
VREF
SENSE
CAPB, CAPT
Junction Temperature
Storage Temperature
Lead Temperature
(10 sec)
Min
–
0.3
–
0.3
–
0.3
–
6.5
–
0.3
–
0.3
–
0.3
Max
+6.5
+6.5
+0.3
+6.5
+6.5
+0.3
+0.3
Units
V
V
V
V
V
V
V
DVSS
DRVSS
–
0.3
–
0.3
DVDD + 0.3
DRVDD
+ 0.3 V
V
AVSS
AVSS
AVSS
AVSS
–
0.3
–
0.3
–
0.3
–
0.3
AVDD
+ 0.3
AVDD
+ 0.3
AVDD
+ 0.3
AVDD + 0.3
+150
+150
V
V
V
V
°
C
°
C
–
65
+300
°
C
*
Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum ratings
for extended periods may effect device reliability.
WARNING!
ESD SENSITIVE DEVICE
SWITCHING SPECIFICATIONS
Parameters
Symbol
AD9260
Units
Clock Period
Data Available (DAV) Period
Data Invalid
Data Setup Time
Clock Pulsewidth High
Clock Pulsewidth Low
Data Hold Time
RESET
to DAV Delay
CLOCK to DAV Delay
Three-State Output Disable Time
Three-State Output Enable Time
t
C
t
DAV
t
DI
t
DS
t
CH
t
CL
t
H
t
RES
–
DAV
t
CLK
–
DAV
t
OD
t
OE
50
t
C
×
Mode
40% t
DAV
t
DAV
–
t
H
–
t
DI
22.5
22.5
3.5
10
15
8
45
ns min
ns min
ns max
ns min
ns min
ns min
ns min
ns typ
ns typ
ns typ
ns typ
Specifications subject to change without notice.
(AVDD = +5 V, DVDD = +5 V, C
L
= 20 pF, T
MIN
to T
MAX
unless otherwise noted)
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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