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參數(shù)資料
| 型號： | AD9260EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | High-Speed Oversampling CMOS ADC with 16-Bit Resolution at a 2.5 MHz Output Word Rate |
| 中文描述： | 高速16位分辨率在2.5 MHz的輸出字速率采樣的CMOS模數(shù)轉(zhuǎn)換器 |
| 文件頁數(shù)： | 22/36頁 |
| 文件大?。?/td> | 572K |
| 代理商： | AD9260EB |
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AD9260
–22–
REV. B
where
q
1 and
q
2 are the individual charges stored on capacitors
CS1 and CS2 respectively, and
CS
is the capacitance value of
CS1 and CS2. When capacitors CS1 and CS2 are connected to
the Analog Modulator during the preceding
“
precharge
”
clock
phase, the capacitors are precharged equal to an approximation
of a previous sample of the input signal. Consequently the
differential charge on these capacitors while CLK is high is
given in the following equation,
Q
(
n
–
1) =
CS
×
VCORE(delay)
+
CS
×
Vdelta
where
VCORE
(
delay
) is the value of VCORE sampled during a
previous period of CLK, and
Vdelta
is the sigma-delta error
voltage left on the capacitors. Vdelta is a natural artifact of the
sigma-delta feedback techniques utilized in the Analog Modula-
tor
of the AD9260
.
It is a small random voltage term that
changes every clock period and varies from 0 to
±
0.05
×
VREF.
The analog circuitry used to drive the input pins of the AD9260
must respond to the charge glitch that occurs when capacitors
CS1 and CS2 are connected to input pins VINA and VINB. This
circuitry must provide additional charge, qdelta, to capacitors
CS1 and CS2, which is the difference between the precharged
value, Q(n
–
1), and the new value, Q(n), as given in the follow-
ing equation,
Qdelta
=
Q
(
n
)
–
Q
(
n
–
1)
Qdelta
=
CS
×
[
VCORE
–
VCORE(delay)
+
Vdelta
]
(7)
(8)
(9)
DRIVING THE INPUT
Transient Response
The charge glitch occurs once at the beginning of every period
of the input CLK (falling edge), and the sample is taken on
capacitors CS1 and CS2 exactly one-half period later (rising
edge). Figure 56 presents a typical input waveform applied to
input Pins VINA and VINB of the AD9260.
CLOCK
VINA-VINB
TRACK SAMPLE TRACK SAMPLE TRACK SAMPLE TRACK SAMPLE
Figure 56. Typical Input Waveform
Figure 56 illustrates the effect of the charge glitch when a source
with nonzero output impedance is used to drive the input pins.
This source must be capable of settling from the charge glitch in
one-half period of the CLK. Unfortunately, the MOS switches
used in any CMOS-switched capacitor circuit (including those
in the AD9260) include nonlinear parasitic junction capaci-
tances connected to their terminals. Figure 55 also illustrates
the parasitic capacitances, Cpa1, Cpb1, Cpa2 and Cpb2, associ-
ated with the input switches.
Parasitic capacitor Cpa1 and Cpa2 are always connected to Pins
VINA and VINB and therefore do not contribute to the glitch
energy. Parasitic capacitors Cpb1 and Cpb2, on the other hand,
cause a charge glitch that adds to that of input capacitors CS1
and CS2 when they are connected to input Pins VINA and
VINB. The nonlinear junction capacitance of Cpb1 and Cpb2
cause charge glitch energy that is nonlinearily related to the
input signal. Therefore, linear settling is difficult to achieve
unless the input source completely settles during one-half
period of CLK. A portion of the glitch impulse energy
“
kicked
”
back at the source is not linearly related to the input signal.
Therefore, the best way to ensure that the input signal settles
linearly is to use wide bandwidth circuitry, which settles as
completely as possible from the glitch during one-half period of
the CLK.
The AD9260 utilizes a proprietary clock-boosted boot-strapping
technique to reduce the nonlinear parasitic capacitances of the
internal CMOS switches. This technique improves the linearity
of the input switches and reduces the nonlinear parasitic capaci-
tance. Thus, this technique reduces the nonlinear glitch energy.
The capacitance values for the input capacitors and parasitic
capacitors for the input structure of the AD9260, as illustrated
in Figure 55, are listed as follows.
CS = 3.2 pF, Cpa = 6 pF, Cpb = 1 pF (where CS is the capaci-
tance value of capacitors CS1 and CS2, Cpa is the value of
capacitors Cpa1 and Cpa2, and Cpb is the value of capacitors
Cpb1 and Cpb2). The total capacitance at each input pin is
C
IN
= CS + Cpa + Cpb = 10.2 pF.
Input Driver Considerations
The optimum noise and distortion performance of the AD9260 can
ONLY be achieved when the AD9260 is driven differentially with a
4 V input span .
Since not all applications have a signal precon-
ditioned for differential operation, there is often a need to per-
form a single-ended-to-differential conversion. In the case of the
AD9260, a single-ended-to-differential conversion is best realized
using a differential op amp driver. Although a transformer will
perform a similar function for ac signals, its usefulness is pre-
cluded by its inability to directly drive the AD9260 and thus the
additional requirement of an active low noise, low distortion
buffer stage.
Single-Ended-to-Differential Op Amp Driver
There are two single-ended-to-differential op amp driver cir-
cuits useful for driving the AD9260. The first circuit, shown in
Figure 57, uses the AD8138 and represents the best choice in
most applications. The AD8138 is a low-distortion differential
ADC driver designed to convert a ground-referenced single-
ended input signal to a differential output signal with a specified
common-mode level for dc-coupling applications. It is capable
of maintaining the typical THD and SFDR performance of the
AD9260 with only a slight degradation in its noise performance
in the 8
×
mode (i.e., SNR of 85 dB
–
86 dB).
In this application, the AD8138 is configured for unity gain and
its common-mode output level is set to 2.5 V (i.e., VREF of the
AD9260) to maximize its output headroom while operating from a
single supply. Note, single-supply operation has the benefit of
not requiring an input protection network for the AD9260 in
dc-coupled applications. A simple R-C network at the output is
used to filter out high-frequency noise from the AD8138. Recall,
the AD9260
’
s small signal bandwidth is 75 MHz, hence any
noise falling within the baseband bandwidth of the AD9260
defined by its sample and decimation rate, as well as
“
images
”
of its baseband response occurring at multiples of the sample
rate, will degrade its overall noise performance.
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