參數(shù)資料
型號(hào)： AD9260EB
廠商： Analog Devices, Inc.
英文描述： High-Speed Oversampling CMOS ADC with 16-Bit Resolution at a 2.5 MHz Output Word Rate
中文描述： 高速16位分辨率在2.5 MHz的輸出字速率采樣的CMOS模數(shù)轉(zhuǎn)換器
文件頁(yè)數(shù)： 21/36頁(yè)
文件大?。?/td> 572K
代理商： AD9260EB
AD9260
–21–
REV. B
A/D core. The scale factor of this reference buffer is 0.8. Conse-
quently, the maximum input voltage to the A/D core is +0.8
×
VREF. The minimum input voltage to the A/D core is auto-
matically defined to be
–
0.8
×
VREF. With this scale factor, the
maximum differential input span of 4 V p-p is obtained with a
VREF voltage of 2.5 V. A smaller differential input span may be
obtained by using a VREF voltage of less than 2.5 V at the
expense of ac performance (refer to Figure 46).
A/D CORE
+0.8 VREF
–
0.8 VREF
16
+
–
VINA
VINB
Figure 54. Simplified Input Model
INPUT SPAN
The AD9260 is implemented with a differential input structure.
This structure allows the common-mode level (average voltage
of the two input pins) of the input signal to be varied indepen-
dently of the input span of the converter over a wide range, as
shown in Figure 44. Specifically, the input to the
A/D core is
the difference of the voltages applied at the VINA and VINB
input pins. Therefore, the equation,
VCORE
=
VINA–VINB
defines the output of the differential input stage and provides
the input to the A/D core.
The voltage,
VCORE
, must satisfy the condition,
–
0.8
×
VREF
≤
VCORE
≤
+0.8
×
VREF
where
VREF
is the voltage at the VREF pin.
(1)
(2)
INPUT COMPLIANCE RANGE
In addition to the limitations on the differential span of the
input signal indicated in Equation 2, an additional limitation is
placed on the inputs by the analog input structure of the AD9260.
The analog input structure bounds the valid operating range for
VINA and VINB. The condition,
AVSS
+0.5
V
<
VINA
<
AVDD
–
0.5
V
AVSS
+0.5
V
<
VINB
<
AVDD
+ 0.5
V
where
AVSS
is nominally 0 V and
AVDD
is nominally +5 V,
defines this requirement. Thus the valid inputs for
VINA
and
VINB
are any combination that satisfies both Equations 2 and
3. Note, the clock clamping method used in the differential
driver circuit shown in Figure 57 is sufficient for protecting the
AD9260 in an undervoltage condition.
For additional information showing the relationships between
VINA, VINB, VREF and the digital output of the AD9260, see
Table V.
Refer to Table IV for a summary of the various analog input
and reference configurations.
(3)
ANALOG INPUT OPERATION
The analog input structure of the AD9260 is optimized to meet
the performance requirements for some of the most demanding
communication and data acquisition applications. This input
structure is composed of a switched-capacitor network that
samples the input signal applied to pins VINA and VINB on
every rising edge of the CLK pin. The input switched capaci-
tors are charged to the input voltage during each period of
CLK. The resulting charge, q, on these capacitors is equal to
C
×
V
IN
, where C is the input capacitor. The change in charge
on these capacitors, delta q, as the capacitors are charged from a
previous sample of the input signal to the next sample, is ap-
proximated in the following equation,
delta q
~ C
×
deltaV
N
=
C
×
(
V
N
–
V
N
–
2
)
where
V
N
represents the present sample of the input signal and
V
N
–
2
represents the sample taken two clock cycles earlier. The
average current flow into the input (provided from an external
source) is given in the following equation,
I
=
delta q/T
~
C
×
(
V
N
–
V
N
–
2
)
×
f
CLOCK
where
T
represents the period of CLK and
f
CLOCK
represents the
frequency of CLK. Equations 4 and 5 provide simplifying ap-
proximations of the operation of the analog input structure of
the AD9260. A more exact, detailed description and analysis of
the input operation is provided below.
(4)
(5)
ANALOG
MODULATOR
VINA
VINB
SS1
SS2
CS1
CS2
SS3
SH1
SS4
SH2
SH3
SH4
CPB1
CPB2
CPA1
CPA2
Figure 55. Detailed Analog Input Structure
Figure 55 illustrates the analog input structure of the AD9260.
For the moment, ignore the presence of the parasitic capacitors
CPA and CPB. The effects of these parasitic capacitors will be
discussed near the end of this section. The switched capacitors,
CS1 and CS2, sample the input voltages applied on pins VINA
and VINB. These capacitors are connected to input pins VINA
and VINB when CLK is low. When CLK rises, a sample of the
input signal is taken on capacitors CS1 and CS2. When CLK is
high, capacitors CS1 and CS2 are connected to the Analog
Modulator
.
The modulator precharges capacitors CS1 and CS2
to minimize the amount of charge required from any circuit
used in combination with the AD9260 to drive input pins VINA
and VINB. This reduces the input drive requirements of the
analog circuitry driving pins VINA and VINB. The Analog
Modulator precharges the voltages across capacitors CS1 and
CS2, approximately equal to a delayed version of the input
signal. When capacitors CS1 and CS2 are connected to input
pins VINA and VINB, the differential charge, Q(n), on these
capacitors is given in the following equation,
Q
(
n
) =
q
1
–
q
2 =
CS
×
VCORE
(6)
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