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參數(shù)資料
| 型號： | AD9260EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | High-Speed Oversampling CMOS ADC with 16-Bit Resolution at a 2.5 MHz Output Word Rate |
| 中文描述： | 高速16位分辨率在2.5 MHz的輸出字速率采樣的CMOS模數(shù)轉(zhuǎn)換器 |
| 文件頁數(shù)： | 29/36頁 |
| 文件大?。?/td> | 572K |
| 代理商： | AD9260EB |
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AD9260
–29–
REV. B
to simplify the layout of the decoupling capacitors and provide
the shortest possible PCB trace lengths. The AD9260/EB power
plane layout, shown in Figure 77 depicts a typical arrangement
using a multilayer PCB.
The digital activity on the AD9260 chip falls into two general
categories: digital logic, and output drivers. The internal digital
logic draws surges of current, mainly during the clock transi-
tions. The output drivers draw large current impulses while the
output bits are changing. The size and duration of these cur-
rents are a function of the load on the output bits: large capaci-
tive loads are to be avoided. Note that the digital logic of the
AD9260 is referenced DVDD while the output drivers are refer-
enced to DRVDD. Also note that the SNR performance of the
AD9260 remains independent of the digital or driver supply
setting.
The decoupling shown in Figure 68, a 0.1
μ
F ceramic chip
capacitor, is appropriate for a reasonable capacitive load on the
digital outputs (typically 20 pF on each pin). Applications
involving greater digital loads should consider increasing the
digital decoupling proportionally, and/or using external buffers/
latches.
0.1 F
DVDD
DVSS
AD9260
DRVDD
DRVSS
0.1 F
3
1
6
5
Figure 68. Digital Supply Decoupling
A complete decoupling scheme will also include large tantalum
or electrolytic capacitors on the PCB to reduce low-frequency
ripple to negligible levels. Refer to the AD9260/EB schematic
and layouts in
Figures 73
–
77 for more information regarding the
placement of decoupling capacitors.
An alternative layout and decoupling scheme is shown in Figure
69. This layout and decoupling scheme is well suited for appli-
cations in which multiple AD9260s are located on the same PC
board and/or the AD9260 is part of a multicard mixed signal
system in which grounds are tied back at the system supplies
(i.e., star ground configuration). In this case, the AD9260 is
treated as an analog component in which its analog (i.e.,
AVDD) and digital (DVDD and DRVDD) supplies are derived
from the systems +5 V analog supply and all of the AD9260
’
s
ground pins are tied directly to the analog ground plane which
resides directly underneath the IC.
Referring to Figure 69, each supply pin is directly decoupled to
their respective ground pin or analog ground plane via a ceramic
0.1
μ
F chip capacitor. Surface mount ferrite beads are used to
isolate the analog (AVDD), digital (DVDD), and driver supplies
(DRVDD) of the AD9260 from the +5 V power buss. Properly
selected ferrite beads can provide more than 40 dB of isolation
from high-frequency switching transients originating from AD9260
supply pins. Further noise immunity from noise is provided by
the inherent power-supply rejection of the AD9260 as shown in
Figure 64. If digital operation at 3 V is desirable for power sav-
ings and or to provide for a 3 V digital logic interface, a 5 V to
3 V linear regulator can be used to drive DVDD and/or DRVDD.
A more complete discussion on this layout and decoupling scheme
can be found in Chapter 7, pages 7-27 through 7-55 of the High
Speed Design Techniques seminar book, which is available at
www.analog.com/support/frames/lin_frameset.hml
.
0.1 F
10 F
0.1 F
FERRITE
BEAD CORE*
VA
SAMPLING CLOCK
GENERATOR
AD9260
0.1 F
DVDD
DVSS
AVDD
AVSS
AVDD
AVSS
AVDD
AVSS
DRVDD
DRVSS
CLK
BUFFER
LATCH
BITS 1
–
16,
DAV
V
D
INSERT 5/3 VOLT LINEAR REGULATOR
FOR 3 OR 3.3V DIGITAL OPERATION
0.1 F
0.1 F
Figure 69.
AD9260 EVALUATION BOARD
GENERAL DESCRIPTION
The AD9260 Evaluation Board is designed to provide an easy
and flexible method of exercising the AD9260 and demonstrate
its performance to data sheet specifications. The evaluation
board is fabricated in four layers: the component layer; the
ground layer; the power layer and the solder layer. The board is
clearly labeled to provide easy identification of components.
Ample space is provided near the analog and clock inputs to
provide additional or alternate signal conditioning.
FEATURES AND USER CONTROL
Jumper Controlled Mode/OSR Selection:
The choice of
Mode/OSR can easily be varied by jumping either JP1,
JP2, JP3 or JP4 as illustrated in Figure 71 within the
Mode/OSR Control Block. To obtain the desired mode
refer to Table VIII.
Table VIII. AD9260 Evaluation Board Mode Select
Mode/OSR
Connect Jumper
1
×
2
×
4
×
8
×
JP4
JP2
JP3
JP1
Selectable Power Bias:
The power consumption of the
AD9260 can be scaled down if the user is able to operate the
device at a lower clock frequency. As illustrated in Figure 71,
pin cups are provided for the external resistor (R2) tied to
the BIAS pin of the AD9260. Table IX defines the recom-
mended resistance for a given clock speed to obtain the de-
sired power consumption.
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相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9260-EB | 制造商:Analog Devices 功能描述:Evaluation Board For AD9260 制造商:Analog Devices 功能描述:DEV TOOLS, EVAL BD FOR AD9260 - Bulk |
| AD9261-10EBZ | 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開發(fā)工具 16Bit 10 MHz Sigma Delta ADC EB RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| AD9261BCPZ-10 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16Bit 10 MHz Sigma Delta ADC RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風格: 封裝 / 箱體: |
| AD9261BCPZRL7-10 | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16Bit 10 MHz Sigma Delta ADC RoHS:否 制造商:Analog Devices 通道數(shù)量: 結(jié)構(gòu): 轉(zhuǎn)換速率: 分辨率: 輸入類型: 信噪比: 接口類型: 工作電源電壓: 最大工作溫度: 安裝風格: 封裝 / 箱體: |
| AD9262-10EBZ | 制造商:Analog Devices 功能描述:Evaluation Board For AD9262BCPZ10 制造商:Analog Devices 功能描述:EVALUATION BOARD FOR AD9262BCPZ-10 - Boxed Product (Development Kits) 制造商:Analog Devices 功能描述:BOARD EVALUATION 10MHZ AD9262 制造商:Analog Devices 功能描述:A/D Converter Eval. Board 制造商:Analog Devices 功能描述:AD9262, ADC, SPI, EVALUATION BOARD; Silicon Manufacturer:Analog Devices; Silicon Core Number:AD9262; Kit Application Type:Data Converter; Application Sub Type:ADC; Kit Contents:Software, Evaluation Board; MSL:MSL 3 - 168 hours 制造商:Analog Devices 功能描述:AD9262, ADC, SPI, EVALUATION BOARD; Silicon Manufacturer:Analog Devices; Silicon Core Number:AD9262; Kit Application Type:Data Converter; Application Sub Type:ADC; Kit Contents:Software, Evaluation Board; MSL:MSL 3 - 168 hours ;RoHS Compliant: Yes |
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