參數(shù)資料
型號(hào)： AD9260EB
廠商： Analog Devices, Inc.
英文描述： High-Speed Oversampling CMOS ADC with 16-Bit Resolution at a 2.5 MHz Output Word Rate
中文描述： 高速16位分辨率在2.5 MHz的輸出字速率采樣的CMOS模數(shù)轉(zhuǎn)換器
文件頁(yè)數(shù)： 28/36頁(yè)
文件大?。?/td> 572K
代理商： AD9260EB
AD9260
–28–
REV. B
Digital Output Driver Considerations (DRVDD)
The AD9260 output drivers can be configured to interface with
+5 V or 3.3 V logic families by setting DRVDD to +5 V or 3.3 V
respectively. The AD9260 output drivers in each mode are
appropriately sized to provide sufficient output current to drive
a wide variety of logic families. However, large drive currents
tend to cause glitches on the supplies and may affect SINAD
performance. Applications requiring the AD9260 to drive large
capacitive loads or large fanout may require additional decou-
pling capacitors on DRVDD. The addition of external buffers or
latches helps reduce output loading while providing effective
isolation from the databus.
Clock Input and Considerations
The AD9260 internal timing uses the two edges of the clock
input to generate a variety of internal timing signals. The clock
input must meet or exceed the minimum specified pulse width
high and low (t
CH
and t
CL
) specifications for the given A/D as
defined in the Switching Specifications at the beginning of the
data sheet to meet the rated performance specifications. For
example, the clock input to the AD9260 operating at 20 MSPS
may have a duty cycle between 45% to 55% to meet this timing
requirement since the minimum specified t
CH
and t
CL
is 22.5 ns.
For clock rates below 20 MSPS, the duty cycle may deviate from
this range to the extent that both t
CH
and t
CL
are satisfied.
All high-speed high-resolution A/Ds are sensitive to the quality of
the clock input. The degradation in SNR at a given full-scale
input frequency (f
IN
) due to only aperture jitter (t
A
) can be calcu-
lated with the following equation:
SNR
= 20 log
10
[1/(2
π
f
IN
t
A
)
]
In the equation, the rms aperture jitter, t
A
, represents the root-
sum square of all the jitter sources which include the clock input,
analog input signal, and A/D aperture jitter specification. For
example, if a 500 kHz full-scale sine wave is sampled by an A/D
with a total rms jitter of 15 ps, the SNR performance of the A/D
will be limited to 86.5 dB.
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the
AD9260. In fact, the CLK input buffer is internally powered
from the AD9260
’
s analog supply, AVDD. Thus the CLK logic
high and low input voltage levels are +3.5 V and +1.0 V, respec-
tively. Supplies for clock drivers should be separated from the
A/D output driver supplies to avoid modulating the clock signal
with digital noise. Low jitter crystal controlled oscillators make
the best clock sources. If the clock is generated from another type
of source (by gating, dividing, or other method), it should be
retimed by the original clock at the last step.
GROUNDING AND DECOUPLING
Analog and Digital Grounding
Proper grounding is essential in any high-speed, high-resolution
system. Multilayer printed circuit boards (PCBs) are recom-
mended to provide optimal grounding and power schemes. The
use of ground and power planes offers distinct advantages:
1. The minimization of the loop area encompassed by a signal
and its return path.
2. The minimization of the impedance associated with ground
and power paths.
3. The inherent distributed capacitor formed by the power plane,
PCB insulation, and ground plane.
These characteristics result in both a reduction of electro-
magnetic interference (EMI) and an overall improvement in
performance.
It is important to design a layout that prevents noise from coupling
onto the input signal. Digital signals should not be run in parallel
with input signal traces and should be routed away from the
input circuitry. While the AD9260 features separate analog and
digital ground pins, it should be treated as an analog component.
The AVSS, DVSS and DRVSS pins must be joined together directly
under the AD9260
. A solid ground plane under the A/D is ac-
ceptable if the power and ground return currents are man-
aged carefully. Alternatively, the ground plane under the A/D
may contain serrations to
steer
currents in predictable directions
where cross-coupling between analog and digital would other-
wise be unavoidable. The AD9260/EB ground layout, shown in
Figure
76, depicts the serrated type of arrangement. The analog
and digital grounds are connected by a jumper below the A/D.
Analog and Digital Supply Decoupling
The AD9260 features separate analog, digital, and driver supply
and ground pins, helping to minimize digital corruption of sen-
sitive analog signals.
Figure 66 shows the power supply rejection ratio vs. frequency
for a 200 mV p-p ripple applied to AVDD, DVDD, and DAVDD.
FREQUENCY
–
kHz
90
10000
P
–
100
1000
10
1
85
80
75
70
65
60
55
50
45
40
DVDD & DRVDD
AVDD
Figure 66. AD9260 PSRR vs. Frequency (8
×
Mode)
In general, AVDD, the analog supply, should be decoupled to
AVSS, the analog common, as close to the chip as physically
possible. Figure 67 shows the recommended decoupling for the
analog supplies; 0.1
μ
F ceramic chip capacitors should provide
adequately low impedance over a wide frequency range. Note
that the AVDD and AVSS pins are co-located on the AD9260
0.1 F
AVDD
AVSS
AD9260
0.1 F
AVDD
AVSS
0.1 F
AVDD
AVSS
4
3
28
29
38
44
Figure 67. Analog Supply Decoupling
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