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參數(shù)資料
| 型號： | AD7655ASTZRL |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 28/28頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 16BIT 4CHAN 48LQFP |
| 標準包裝： | 2,000 |
| 系列： | PulSAR® |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 1M |
| 數(shù)據(jù)接口： | 串行，并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 135mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-LQFP |
| 供應(yīng)商設(shè)備封裝： | 48-LQFP（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 2 個差分，單極 |
| 配用： | EVAL-AD7655CBZ-ND - BOARD EVALUATION FOR AD7655 |
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AD7655
Rev. B | Page 9 of 28
Pin No.
Mnemonic
Type1
Description
15
D[6]
DI/O
When SER/PAR is LOW, this output is used as Bit 6 of the parallel port data output bus.
or INVSCLK
When SER/PAR is HIGH, this input, part of the serial port, is used to invert the SCLK signal. It is active in
both master and slave modes.
16
D[7]
DI/O
When SER/PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output Bus.
or RDC/SDIN
When SER/PAR is HIGH, this input, part of the serial port, is used as either an external data input or a
read mode selection input, depending on the state of EXT/INT.
When EXT/INT is HIGH, RDC/SDIN can be used as a data input to daisy-chain the conversion results
from two or more ADCs onto a single SDOUT line. The digital data level on SDIN is output on SDOUT
with a delay of 32 SCLK periods after the initiation of the read sequence.
When EXT/INT is LOW, RDC/SDIN is used to select the read mode. When RDC/SDIN is HIGH, the
previous data is output on SDOUT during conversion. When RDC/SDIN is LOW, the data can be output
on SDOUT only when the conversion is complete.
17
OGND
P
Input/Output Interface Digital Power Ground.
18
OVDD
P
Input/Output Interface Digital Power. Nominally at the same supply as the supply of the host interface
(5 V or 3 V).
19, 36
DVDD
P
Digital Power. Nominally at 5 V.
21
D[8]
DO
When SER/PAR is LOW, this output is used as Bit 8 of the Parallel Port Data Output Bus.
or SDOUT
When SER/PAR is HIGH, this output, part of the serial port, is used as a serial data output synchronized
to SCLK. Conversion results are stored in a 32-bit on-chip register. The AD7655 provides the two
conversion results, MSB first, from its internal shift register. The order of channel outputs is controlled
by A/B. In serial mode, when EXT/INT is LOW, SDOUT is valid on both edges of SCLK.
In serial mode, when EXT/INT is HIGH:
If INVSCLK is LOW, SDOUT is updated on the SCLK rising edge and valid on the next falling edge.
If INVSCLK is HIGH, SDOUT is updated on the SCLK falling edge and valid on the next rising edge.
22
D[9]
DI/O
When SER/PAR is LOW, this output is used as Bit 9 of the Parallel Port Data Output Bus.
or SCLK
When SER/PAR is HIGH, this pin, part of the serial port, is used as a serial data clock input or output,
depends upon the logic state of the EXT/INT pin. The active edge where the data SDOUT is updated
depends on the logic state of the INVSCLK pin.
23
D[10]
DO
When SER/PAR is LOW, this output is used as Bit 10 of the Parallel Port Data Output Bus.
or SYNC
When SER/PAR is HIGH, this output, part of the serial port, is used as a digital output frame
synchronization for use with the internal data clock (EXT/INT = Logic LOW).
When a read sequence is initiated and INVSYNC is LOW, SYNC is driven HIGH and frames SDOUT. After
the first channel is output, SYNC is pulsed LOW. When a read sequence is initiated and INVSYNC is
HIGH, SYNC is driven LOW and remains LOW while SDOUT output is valid. After the first channel is
output, SYNC is pulsed HIGH.
24
D[11]
DO
When SER/PAR is LOW, this output is used as Bit 11 of the Parallel Port Data Output Bus.
or RDERROR
When SER/PAR is HIGH and EXT/INT is HIGH, this output, part of the serial port, is used as an
incomplete read error flag. In slave mode, when a data read is started but not complete when the
following conversion is complete, the current data is lost and RDERROR is pulsed HIGH.
25 to 28
D[12:15]
DO
Bit 12 to Bit 15 of the parallel port data output bus. When SER/PAR is HIGH, these outputs are in high
impedance.
29
BUSY
DO
Busy Output. Transitions HIGH when a conversion is started and remains HIGH until the two
conversions are complete and the data is latched into the on-chip shift register. The falling edge of
BUSY can be used as a data ready clock signal.
30
EOC
DO
End of Convert Output. Goes LOW at each channel conversion.
31
RD
DI
Read Data. When CS and RD are both LOW, the interface parallel or serial output bus is enabled.
32
CS
DI
Chip Select. When CS and RD are both LOW, the interface parallel or serial output bus is enabled. CS is
also used to gate the external serial clock.
33
RESET
DI
Reset Input. When set to a logic HIGH, reset the AD7655. Current conversion, if any, is aborted. If not
used, this pin could be tied to DGND.
34
PD
DI
Power-Down Input. When set to a logic HIGH, power consumption is reduced and conversions are
inhibited after the current conversion is completed.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD7655SCP-EP-RL | 制造商:Analog Devices 功能描述:ADC Single SAR 1Msps 16-bit Parallel/Serial 48-Pin LFCSP EP T/R 制造商:Analog Devices 功能描述:LOW COST 4-CHANNEL 1 MSPS 16-BIT ADC - Tape and Reel 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述:IC ADC 16B PAR/SRL 1MSPS 48LFCSP 制造商:Analog Devices 功能描述:Analog to Digital Converters - ADC 4Ch 1MSPS 16-Bit Low Cost 制造商:Analog Devices 功能描述:CONVERTER - ADC |
| AD7656 | 制造商:AD 制造商全稱:Analog Devices 功能描述:250 kSPS, 6-Channel,Simultaneous Sampling, Bipolar 12/14/16-Bit ADC |
| AD7656-1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:250 kSPS, 6-Channel, Simultaneous Sampling, Bipolar, 16-/14-/12-Bit ADC |
| AD7656A-1BSTZ | 功能描述:16 Bit Analog to Digital Converter 6 Input 6 SAR 64-LQFP (10x10) 制造商:analog devices inc. 系列:iCMOS? 包裝:托盤 零件狀態(tài):有效 位數(shù):16 采樣率（每秒）:250k 輸入數(shù):6 輸入類型:單端 數(shù)據(jù)接口:SPI，并聯(lián)，DSP 配置:S/H-ADC 無線電 - S/H:ADC:1:1 A/D 轉(zhuǎn)換器數(shù):6 架構(gòu):SAR 參考類型:外部， 內(nèi)部 電壓 - 電源，模擬:5V 電壓 - 電源，數(shù)字:5V 特性:仿真采樣，真正的雙極性 工作溫度:-40°C ~ 85°C 封裝/外殼:64-LQFP 供應(yīng)商器件封裝:64-LQFP（10x10） 標準包裝:1 |
| AD7656A-1BSTZ-RL | 功能描述:16 Bit Analog to Digital Converter 6 Input 6 SAR 64-LQFP (10x10) 制造商:analog devices inc. 系列:iCMOS? 包裝:帶卷（TR） 零件狀態(tài):有效 位數(shù):16 采樣率（每秒）:250k 輸入數(shù):6 輸入類型:單端 數(shù)據(jù)接口:SPI，并聯(lián)，DSP 配置:S/H-ADC 無線電 - S/H:ADC:1:1 A/D 轉(zhuǎn)換器數(shù):6 架構(gòu):SAR 參考類型:外部， 內(nèi)部 電壓 - 電源，模擬:5V 電壓 - 電源，數(shù)字:5V 特性:仿真采樣，真正的雙極性 工作溫度:-40°C ~ 85°C 封裝/外殼:64-LQFP 供應(yīng)商器件封裝:64-LQFP（10x10） 標準包裝:1,500 |
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