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| 型號(hào)： | A14100A-STDCQG256B |
| 元件分類： | FPGA |
| 英文描述： | FPGA, 1377 CLBS, 30000 GATES, 85 MHz, CQFP256 |
| 封裝： | CERAMIC, QFP-256 |
| 文件頁數(shù)： | 16/54頁 |
| 文件大小： | 343K |
| 代理商： | A14100A-STDCQG256B |
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RadTolerant FPGAs
v3.1
1-19
RT1280A, A1280A Timing Characteristics
Table 1-12 RT1280A, A1280A Logic Module
Worst-Case Military Conditions, VCC = 4.5 V, TJ = 125°C
–1 Speed
Std Speed
Parameter
Description
Min.
Max.
Min.
Max.
Units
Logic Module Propagation Delays1
tPD1
Single Module
5.2
6.1
ns
tCO
Sequential Clock-to-Q
5.2
6.1
ns
tGO
Latch G-to-Q
5.2
6.1
ns
tRS
Flip-Flop (Latch) Reset-to-Q
5.2
6.1
ns
Logic Module Predicted Routing Delays2
tRD1
FO=1 Routing Delay
2.4
2.8
ns
tRD2
FO=2 Routing Delay
3.4
4.0
ns
tRD3
FO=3 Routing Delay
4.2
4.9
ns
tRD4
FO=4 Routing Delay
5.1
6.0
ns
tRD8
FO=8 Routing Delay
9.2
10.8
ns
Logic Module Sequential Timing 3, 4
tSUD
Flip-Flop (Latch) Data Input Setup
0.5
ns
tHD
Flip-Flop (Latch) Data Input Hold
0.0
ns
tSUENA
Flip-Flop (Latch) Enable Setup
1.3
ns
tHENA
Flip-Flop (Latch) Enable Hold
0.0
ns
tWCLKA
Flip-Flop (Latch) Clock Active Pulse Width
7.4
8.6
ns
tWASYN
Flip-Flop (Latch) Asynchronous Pulse Width
7.4
8.6
ns
tA
Flip-Flop Clock Input Period
16.4
22.1
ns
tINH
Input Buffer Latch Hold
2.5
ns
tINSU
Input Buffer Latch Setup
3.5
ns
tOUTH
Output Buffer Latch Hold
0.0
ns
tOUTSU
Output Buffer Latch Setup
0.5
ns
fMAX
Flip-Flop (Latch) Clock Frequency
60
41
MHz
Notes:
1. For dual-module macros, use tPD1 + tRD1 + tPDn, tCO + tRD1 + tPDn, or tPD1 + tRD1 + tSUD, whichever is appropriate.
2. Routing delays are for typical designs across worst-case operating conditions. These parameters should be used for estimating
device performance. Post-route timing analysis or simulation is required to determine actual worst-case performance. Post-route
timing is based on actual routing delay measurements performed on the device prior to shipment.
3. Data applies to macros based on the S-module. Timing parameters for sequential macros constructed from C-modules can be
obtained from the Timer utility.
4. Setup and hold timing parameters for the input buffer latch are defined with respect to the PAD and the D input. External setup/
hold timing parameters must account for delay from an external PAD signal to the G inputs. Delay from an external PAD signal to
the G input subtracts (adds) to the internal setup (hold) time.
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