參數(shù)資料
型號(hào)： 935246150005
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, UUC
封裝： CHIP ON WAFER
文件頁數(shù)： 68/68頁
文件大?。?/td> 234K
代理商： 935246150005
2000 Jan 04
9
Philips Semiconductors
Product specication
Stand-alone CAN controller
SJA1000
Table 1
BasicCAN address allocation; note 1
Notes
1. It should be noted that the registers are repeated within higher CAN address areas (the most significant bits of the
8-bit CPU address are not decoded: CAN address 32 continues with CAN address 0 and so on).
2. Test register is used for production testing only. Using this register during normal operation may result in undesired
behaviour of the device.
3. Some bits are writeable in reset mode only (CAN mode and CBP).
CAN
ADDRESS
SEGMENT
OPERATING MODE
RESET MODE
READ
WRITE
READ
WRITE
0
control
1
(FFH)
command
(FFH)
command
2
status
status
3
interrupt
interrupt
4
(FFH)
acceptance code
5
(FFH)
acceptance mask
6
(FFH)
bus timing 0
7
(FFH)
bus timing 1
8
(FFH)
output control
9
test
test; note 2
test
test; note 2
10
transmit
buffer
identier (10 to 3)
(FFH)
11
identier (2 to 0),
RTR and DLC
identier (2 to 0),
RTR and DLC
(FFH)
12
data byte 1
(FFH)
13
data byte 2
(FFH)
14
data byte 3
(FFH)
15
data byte 4
(FFH)
16
data byte 5
(FFH)
17
data byte 6
(FFH)
18
data byte 7
(FFH)
19
data byte 8
(FFH)
20
receive
buffer
identier (10 to 3)
21
identier (2 to 0),
RTR and DLC
identier (2 to 0),
RTR and DLC
identier (2 to 0),
RTR and DLC
identier (2 to 0),
RTR and DLC
22
data byte 1
23
data byte 2
24
data byte 3
25
data byte 4
26
data byte 5
27
data byte 6
28
data byte 7
29
data byte 8
30
(FFH)
(FFH)
31
clock divider
clock divider; note 3
clock divider
相關(guān)PDF資料
PDF描述
935230900112 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PDIP28
06NU06NU INNENGEWINDE BSP DREHB G 0.38
08NU06NU INNENGEWINDE BSP DREHB G G 0.38X0.5ZOLL
08NU08NU INNENGEWINDE BSP DREHB G 0.5
08NU10NU INNENGEWINDE BSP DREHB G 0.5X0.63ZOLL
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