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參數(shù)資料
| 型號： | 935246150005 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, UUC |
| 封裝： | CHIP ON WAFER |
| 文件頁數(shù)： | 46/68頁 |
| 文件大?。?/td> | 234K |
| 代理商： | 935246150005 |
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2000 Jan 04
50
Philips Semiconductors
Product specication
Stand-alone CAN controller
SJA1000
6.5
Common registers
6.5.1
BUS TIMING REGISTER 0 (BTR0)
The contents of the bus timing register 0 defines the values of the Baud Rate Prescaler (BRP) and the Synchronization
Jump Width (SJW). This register can be accessed (read/write) if the reset mode is active.
In operating mode this register is read only, if the PeliCAN mode is selected. In BasicCAN mode a ‘FFH’ is reflected.
Table 44 Bit interpretation of bus timing register 0 (BTR0); CAN address 6
6.5.1.1
Baud Rate Prescaler (BRP)
The period of the CAN system clock tscl is programmable and determines the individual bit timing. The CAN system clock
is calculated using the following equation:
tscl =2 × tCLK × (32 × BRP.5 + 16 × BRP.4 + 8 × BRP.3 + 4 × BRP.2 + 2 × BRP.1 + BRP.0 + 1)
where tCLK = time period of the XTAL frequency =
6.5.1.2
Synchronization Jump Width (SJW)
To compensate for phase shifts between clock oscillators of different bus controllers, any bus controller must
re-synchronize on any relevant signal edge of the current transmission. The synchronization jump width defines the
maximum number of clock cycles a bit period may be shortened or lengthened by one re-synchronization:
tSJW =tscl × (2 × SJW.1 + SJW.0 + 1)
6.5.2
BUS TIMING REGISTER 1 (BTR1)
The contents of bus timing register 1 defines the length of the bit period, the location of the sample point and the number
of samples to be taken at each sample point. This register can be accessed (read/write) if the reset mode is active.
In operating mode, this register is read only, if the PeliCAN mode is selected. In BasicCAN mode a ‘FFH’ is reflected.
Table 45 Bit interpretation of bus timing register 1 (BTR1); CAN address 7
6.5.2.1
Sampling (SAM)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SJW.1
SJW.0
BRP.5
BRP.4
BRP.3
BRP.2
BRP.1
BRP.0
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
SAM
TSEG2.2
TSEG2.1
TSEG2.0
TSEG1.3
TSEG1.2
TSEG1.1
TSEG1.0
BIT
VALUE
FUNCTION
SAM
1
triple; the bus is sampled three times; recommended for low/medium speed buses
(class A and B) where ltering spikes on the bus line is benecial
0
single; the bus is sampled once; recommended for high speed buses (SAE class C)
1
f
XTAL
-------------
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