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參數(shù)資料
| 型號(hào)： | 935246150005 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, UUC |
| 封裝： | CHIP ON WAFER |
| 文件頁(yè)數(shù)： | 11/68頁(yè) |
| 文件大?。?/td> | 234K |
| 代理商： | 935246150005 |
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2000 Jan 04
19
Philips Semiconductors
Product specication
Stand-alone CAN controller
SJA1000
Fig.4 Example of the message storage within the RXFIFO.
Message 1 is now available in the receive buffer.
handbook, full pagewidth
MGK618
release
receive
buffer
command
64-byte
FIFO
incoming
messages
message 3
message 2
message 1
29
28
27
26
25
24
23
22
21
20
receive
buffer
window
CAN address
Identifier, remote transmission request bit and data length
code have the same meaning and location as described in
the transmit buffer but within the address range 20 to 29.
As illustrated in Fig.4 the RXFIFO has space for
64 message bytes in total. The number of messages that
can be stored in the FIFO at any particular moment
depends on the length of the individual messages. If there
is not enough space for a new message within the
RXFIFO, the CAN controller generates a data overrun
condition. A message which is partly written into the
RXFIFO, when the data overrun condition occurs, is
deleted. This situation is indicated to the microcontroller
via the status register and the data overrun interrupt, if
enabled and the frame was received without any errors
until the last but one bit of end of frame (RX message
becomes valid).
6.3.9
ACCEPTANCE FILTER
With the help of the acceptance filter the CAN controller is
able to allow passing of received messages to the RXFIFO
only when the identifier bits of the received message are
equal to the predefined ones within the acceptance filter
registers. The acceptance filter is defined by the
acceptance code register (ACR; see Section 6.3.9.1) and
the acceptance mask register (AMR; see Section 6.3.9.2).
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