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| 型號： | 935246150005 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, UUC |
| 封裝： | CHIP ON WAFER |
| 文件頁數(shù)： | 25/68頁 |
| 文件大?。?/td> | 234K |
| 代理商： | 935246150005 |
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2000 Jan 04
31
Philips Semiconductors
Product specication
Stand-alone CAN controller
SJA1000
6.4.6
INTERRUPT REGISTER (IR)
The interrupt register allows the identification of an interrupt source. When one or more bits of this register are set, a CAN
interrupt will be indicated to the CPU. After this register is read by the CPU all bits are reset except for the receive interrupt
bit.
The interrupt register appears to the CPU as a read only memory.
Table 15 Bit interpretation of the interrupt register (IR); CAN address 3
BIT
SYMBOL
NAME
VALUE
FUNCTION
IR.7
BEI
Bus Error Interrupt
1
set; this bit is set when the CAN controller detects
an error on the CAN-bus and the BEIE bit is set
within the interrupt enable register
0
reset
IR.6
ALI
Arbitration Lost Interrupt
1
set; this bit is set when the CAN controller lost the
arbitration and becomes a receiver and the ALIE
bit is set within the interrupt enable register
0
reset
IR.5
EPI
Error Passive Interrupt
1
set; this bit is set whenever the CAN controller has
reached the error passive status (at least one
error counter exceeds the protocol-dened level of
127) or if the CAN controller is in the error passive
status and enters the error active status again and
the EPIE bit is set within the interrupt enable
register
0
reset
IR.4
WUI
Wake-Up Interrupt;
note 1
1
set; this bit is set when the CAN controller is
sleeping and bus activity is detected and the
WUIE bit is set within the interrupt enable register
0
reset
IR.3
DOI
Data Overrun Interrupt
1
set; this bit is set on a ‘0-to-1’ transition of the data
overrun status bit and the DOIE bit is set within
the interrupt enable register
0
reset
IR.2
EI
Error Warning Interrupt
1
set; this bit is set on every change (set and clear)
of either the error status or bus status bits and the
EIE bit is set within the interrupt enable register
0
reset
IR.1
TI
Transmit Interrupt
1
set; this bit is set whenever the transmit buffer
status changes from ‘0-to-1’ (released) and the
TIE bit is set within the interrupt enable register
0
reset
IR.0
RI
Receive Interrupt; note 2
1
set; this bit is set while the receive FIFO is not
empty and the RIE bit is set within the interrupt
enable register
0
reset; no more message is available within the
RXFIFO
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 935230900112 | 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PDIP28 |
| 06NU06NU | INNENGEWINDE BSP DREHB G 0.38 |
| 08NU06NU | INNENGEWINDE BSP DREHB G G 0.38X0.5ZOLL |
| 08NU08NU | INNENGEWINDE BSP DREHB G 0.5 |
| 08NU10NU | INNENGEWINDE BSP DREHB G 0.5X0.63ZOLL |
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參數(shù)描述 |
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| 935252-5 | 制造商:C-H 功能描述:935252-5 |
| 935257650112 | 制造商:NXP Semiconductors 功能描述:SUB ONLY ICSUBS TO 935257650112 |
| 935260093112 | 制造商:NXP Semiconductors 功能描述:IC AVIC ADV BASESTATION 14SOIC |
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