- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄24793 > 935230900112 (NXP SEMICONDUCTORS) 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PDIP28 PDF資料下載
參數(shù)資料
| 型號(hào)： | 935230900112 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 2 CHANNEL(S), 1M bps, LOCAL AREA NETWORK CONTROLLER, PDIP28 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-28 |
| 文件頁數(shù)： | 8/68頁 |
| 文件大小： | 234K |
| 代理商： | 935230900112 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁當(dāng)前第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁
2000 Jan 04
16
Philips Semiconductors
Product specication
Stand-alone CAN controller
SJA1000
Notes
1. When the transmit error counter exceeds the limit of 255 [the bus status bit is set to logic 1 (bus-off)] the
CAN controller will set the reset request bit to logic 1 (present) and an error interrupt is generated, if enabled. It will
stay in this mode until the CPU clears the reset request bit. Once this is completed the CAN controller will wait the
minimum protocol-defined time (128 occurrences of the bus-free signal). After that the bus status bit is cleared
(bus-on), the error status bit is set to logic 0 (ok), the error counters are reset and an error interrupt is generated, if
enabled.
2. Errors detected during reception or transmission will affect the error counters according to the CAN 2.0B protocol
specification. The error status bit is set when at least one of the error counters has reached or exceeded the CPU
warning limit of 96. An error interrupt is generated, if enabled.
3. If both the receive status and the transmit status bits are logic 0 (idle) the CAN-bus is idle.
4. The transmission complete status bit is set to logic 0 (incomplete) whenever the transmission request bit is set to
logic 1. The transmission complete status bit will remain at logic 0 (incomplete) until a message is transmitted
successfully.
5. If the CPU tries to write to the transmit buffer when the transmit buffer status bit is at logic 0 (locked), the written byte
will not be accepted and will be lost without being indicated.
6. When a message that shall be received has passed the acceptance filter successfully (i.e. earliest after arbitration
field), the CAN controller needs space in the RXFIFO to store the message descriptor. Accordingly there must be
enough space for each data byte which has been received. If there is not enough space to store the message, that
message will be dropped and the data overrun condition will be indicated to the CPU only, if this received message
has no errors until the last but one bit of end of frame (message becomes valid).
7. After reading a message stored in the RXFIFO and releasing this memory space with the command release receive
buffer, this bit is cleared. If there is another message available within the FIFO this bit is set again with the next bit
quantum (tscl).
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| 06NU06NU | INNENGEWINDE BSP DREHB G 0.38 |
| 08NU06NU | INNENGEWINDE BSP DREHB G G 0.38X0.5ZOLL |
| 08NU08NU | INNENGEWINDE BSP DREHB G 0.5 |
| 08NU10NU | INNENGEWINDE BSP DREHB G 0.5X0.63ZOLL |
| 08NU12NU | INNENGEWINDE BSP DREHB G0.5X0.75ZOLL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 9352370001 | 功能描述:HEAT SHRINK SLEEVE RoHS:是 類別:線纜，導(dǎo)線 - 管理 >> 標(biāo)簽，標(biāo)記 系列:HT-SCE 標(biāo)準(zhǔn)包裝:250 系列:CM-SCE 標(biāo)簽類型:標(biāo)準(zhǔn) 標(biāo)簽尺寸:2.00" x 0.25"（50.8mm x 6.4mm） 顏色:白 材質(zhì):聚烯烴 適用于相關(guān)產(chǎn)品:點(diǎn)陣打印機(jī) 包裝:* 工作溫度:-55°C ~ 135°C 其它名稱:A105291CM-SCE-TP-1/4-4H-9 |
| 935241-0001 | 制造商: 功能描述: 制造商:DIGITRAN 功能描述: 制造商:undefined 功能描述: |
| 935241-1 | 制造商:DIGITRAN 功能描述: 制造商:DTRAN 功能描述: |
| 935245650125 | 制造商:NXP Semiconductors 功能描述:Inverter 1-Element CMOS 5-Pin TSSOP T/R |
| 935248-90 | 制造商:JANCO 功能描述:935248-90 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。